公开(公告)号：US20240126714A1

公开(公告)日：2024-04-18

申请号：US18397199

申请日：2023-12-27

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F15/167 ,  G06F16/22 ,  H04L69/22

CPC classification number: G06F15/167 ,  G06F16/22 ,  H04L69/22

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

公开(公告)号：US20240073297A1

公开(公告)日：2024-02-29

申请号：US18462321

申请日：2023-09-06

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Alan Michael Judge ,  Erez Izenberg ,  Julien Ridoux ,  Joshua Benjamin Levinson ,  Anthony Nicholas Liguori ,  Nafea Bshara

IPC: H04L67/60 ,  G06F9/50 ,  H04L9/40 ,  H04L67/14

CPC classification number: H04L67/60 ,  G06F9/5038 ,  H04L63/0428 ,  H04L67/14

Abstract: Various embodiments of apparatuses and methods for multi-cast, multiple unicast, and unicast distribution of messages with time synchronized delivery are described. In some embodiments, the disclosed system and methods include a reference timekeeper providing a reference clock to one or more host computing devices. The one or more host computing devices host compute instances, and also contain respective isolated timing hardware outside the control of the compute instances. The isolated timing hardware of the one or more host computing devices then receive respective packets, and obtain the same time to deliver the respective packets. Each isolated timing hardware provides either the packet, or information to access the packet, to its respective destination compute instance subsequent to determining that the same specified time to deliver the packet has occurred. Thus, the respective packets are delivered near simultaneously to the one or more destination compute instances.

公开(公告)号：US11811637B1

公开(公告)日：2023-11-07

申请号：US17456511

申请日：2021-11-24

Applicant: Amazon Technologies, Inc.

Inventor： Noam Katz ,  Amiram Lifshitz ,  Said Bshara ,  Erez Izenberg ,  Jonathan Chocron

IPC: H04L43/106 ,  H04L69/28 ,  H04L69/18

CPC classification number: H04L43/106 ,  H04L69/18 ,  H04L69/28

Abstract: To support different timestamp formats, for example, for different network protocols, an integrated circuit device is provided with a memory that is programmed with multiple instruction sets associated with multiple timestamp formats. Each of the instruction sets contains instructions to generate a timestamp according to a corresponding timestamp format. A compute circuit can generate a formatted timestamp by using a base timestamp input and executing an instruction set selected from the multiple instruction sets stored in the memory.

公开(公告)号：US11606104B1

公开(公告)日：2023-03-14

申请号：US17545846

申请日：2021-12-08

Applicant: Amazon Technologies, Inc.

Inventor： Avigdor Segal ,  Leonid Baryudin ,  Erez Izenberg ,  Erez Sabbag ,  Se Wang Oh ,  Noga Smith

IPC: G06F11/00 ,  H03M13/09 ,  G06F11/14

Abstract: The integrity of transmitted data can be protected by causing that data to be transmitted twice, and calculating protection information (PI) for the data from each transmission. The PI can include information such as a checksum or signature that should have the same value if the data from each transmission is the same. If the PI values are not the same, an error handling procedure can be activated, such as may retry the transmission. For write operations, the data can be transmitted twice from a source to a storage destination, while for read operations, the data can be transmitted to a recipient then sent back from the recipient to the storage device, with PI calculated for each transmission. A component such as a storage processor can perform at least this comparison step. Such approaches can also be used for network transmission or high performance computing.

公开(公告)号：US20230004521A1

公开(公告)日：2023-01-05

申请号：US17901720

申请日：2022-09-01

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F15/167 ,  H04L69/22 ,  G06F16/22

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

公开(公告)号：US11386008B1

公开(公告)日：2022-07-12

申请号：US17018105

申请日：2020-09-11

Applicant: Amazon Technologies, inc.

Inventor： Anna Rom-Saksonov ,  Erez Izenberg ,  Avigdor Segal ,  Jonathan Cohen ,  Nitzan Zisman ,  Noam Attias

IPC: G06F12/0846 ,  G06F12/02 ,  G06F11/10 ,  G06F11/07 ,  G11C15/00 ,  G11C15/04

Abstract: A memory apparatus for detecting false hits in a content-addressable memory (CAM) is disclosed. The memory apparatus includes a controller coupled to the CAM and a memory. The controller receives a search result including an address from the CAM, the address corresponding to a matching entry from a first set of data entries that matches a search tag. The controller provides a read address based on the address to the memory, which returns a second data entry from a second set of data entries corresponding to the read address. The controller receives the read data and generates an error detection result based on a comparison between the second data entry and the search tag.

公开(公告)号：US20220078078A1

公开(公告)日：2022-03-10

申请号：US17473644

申请日：2021-09-13

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Nafea Bshara ,  Christopher Pettey ,  Curtis Karl Ohrt

IPC: H04L12/24 ,  G06F15/78 ,  G06F9/50 ,  G06F9/455

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

公开(公告)号：US11182320B2

公开(公告)日：2021-11-23

申请号：US16918151

申请日：2020-07-01

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F15/76 ,  G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US11099894B2

公开(公告)日：2021-08-24

申请号：US15279164

申请日：2016-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan ,  Christopher Joseph Pettey ,  Erez Izenberg ,  Nafea Bshara

IPC: G06F9/455 ,  G06F9/46 ,  G06F9/50 ,  G06F13/40 ,  G06F9/54

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.

公开(公告)号：US20210182230A1

公开(公告)日：2021-06-17

申请号：US17184507

申请日：2021-02-24

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.