公开(公告)号：US09438053B2

公开(公告)日：2016-09-06

申请号：US13772190

申请日：2013-02-20

申请人： Ross E. Teggatz ,  Ken Moore ,  Edson Calixto ,  Emanuel Stingu

发明人： Ross E. Teggatz ,  Ken Moore ,  Edson Calixto ,  Emanuel Stingu

IPC分类号： H01M10/44 ,  H01M10/46 ,  H02J7/00 ,  H02J7/02 ,  H02J7/35

CPC分类号： H02J7/355 ,  H02J7/0052 ,  H02J7/007 ,  H02J7/025 ,  H02J7/027 ,  H02J7/35 ,  H02J50/00 ,  H02J50/10 ,  H02J50/12 ,  H02S20/30 ,  H02S40/34 ,  H02S40/38

摘要： A scalable energy harvesting system comprising at least one charging control device, at least one energy storage device responsive to the charging control device, at least one energy harvesting device operatively coupled to the charging control device, and a plurality of bus based power connectors operatively coupled to the charging control device.

摘要翻译： 一种可扩展的能量采集系统，包括至少一个充电控制装置，响应于所述充电控制装置的至少一个能量存储装置，至少一个能够操作地耦合到所述充电控制装置的能量收集装置，以及多个基于总线的电力连接器， 到充电控制装置。

公开(公告)号：US07269528B2

公开(公告)日：2007-09-11

申请号：US11139172

申请日：2005-05-28

申请人： David John Baldwin ,  Eric Blackall ,  Joseph Devore ,  Ross E. Teggatz

发明人： David John Baldwin ,  Eric Blackall ,  Joseph Devore ,  Ross E. Teggatz

IPC分类号： G06F15/00

CPC分类号： G11C16/34

摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.

摘要翻译： 一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特定的顺序：（1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

公开(公告)号：US06864702B1

公开(公告)日：2005-03-08

申请号：US10746984

申请日：2003-12-24

申请人： Ross E. Teggatz ,  Reed W. Adams ,  Suribhotla V. Rajasekhar

发明人： Ross E. Teggatz ,  Reed W. Adams ,  Suribhotla V. Rajasekhar

IPC分类号： G01R31/28 ,  G01R31/27

CPC分类号： G01R31/2858

摘要： The present invention provides a system for stress testing an oxide structure to determine that structure's reliability in overstress conditions. The present invention provides an overstress test structure (400) that comprises a first transistor (406), having a first terminal coupled to ground, a second terminal coupled to a control signal (402), and a third terminal coupled to a first end of a first resistive element (412). A first voltage source (414) is coupled to the second end of the first resistive element. A second resistive element (416) is intercoupled between the second end of the first resistive element and ground. A second transistor (418) has a first terminal coupled to the second end of the first resistive element, a second terminal coupled to the first end of the first resistive element, and a third terminal coupled to a first node (420). A third resistive element (422) is intercoupled between the third terminal of the second transistor and ground; and a third transistor (424) has a first terminal coupled (426) to the oxide structure, a second terminal coupled to the first end of the first resistive elerment, and a third terminal coupled to a second voltage source (428).

摘要翻译： 本发明提供了一种用于对氧化物结构进行应力测试以确定该结构在过应力条件下的可靠性的系统。 本发明提供了一种过应力测试结构（400），其包括第一晶体管（406），其具有耦合到地的第一端子，耦合到控制信号（402）的第二端子和耦合到控制信号 第一电阻元件（412）。 第一电压源（414）耦合到第一电阻元件的第二端。 第二电阻元件（416）在第一电阻元件的第二端和地之间相互配合。 第二晶体管（418）具有耦合到第一电阻元件的第二端的第一端子，耦合到第一电阻元件的第一端的第二端子和耦合到第一节点（420）的第三端子。 第三电阻元件（422）在第二晶体管的第三端与地之间相互耦合; 和第三晶体管（424）具有耦合到所述氧化物结构的第一端子（426），耦合到所述第一电阻器的第一端的第二端子和耦合到第二电压源（428）的第三端子。

公开(公告)号：US06696861B1

公开(公告)日：2004-02-24

申请号：US10285900

申请日：2002-11-01

申请人： David J. Baldwin ,  Zbigniew J. Lata ,  Sanmukh M. Patel ,  Ross E. Teggatz

发明人： David J. Baldwin ,  Zbigniew J. Lata ,  Sanmukh M. Patel ,  Ross E. Teggatz

IPC分类号： H03K1716

CPC分类号： H02M3/156 ,  H02M3/1563 ,  H02M3/1588 ,  Y02B70/1466

摘要： A switch mode controller circuit includes: a hysteretic comparator HYST_COMP for monitoring an output of a switch mode circuit; a standard comparator PHASE_COMP for monitoring a phase of the switch mode circuit; a logic block having a first input coupled to a clock signal generator Oscillator, a second input coupled to an output of the hysteretic comparator HYST_COMP, and a third input coupled to an output of the standard comparator PHASE_COMP, wherein the logic block generates switching cycles based on a fixed ON/OFF time during a first part of a cycle and based on a hysteretic control during a second part of the cycle.

摘要翻译： 开关模式控制器电路包括：用于监视开关模式电路的输出的滞后比较器HYST_COMP; 用于监视开关模式电路的相位的标准比较器PHASE_COMP; 逻辑块，其具有耦合到时钟信号发生器振荡器的第一输入，耦合到迟滞比较器HYST_COMP的输出的第二输入和耦合到标准比较器PHASE_COMP的输出的第三输入，其中逻辑块基于 在循环的第一部分期间处于固定的ON / OFF时间，并且基于在循环的第二部分期间的滞后控制。

公开(公告)号：US06674621B2

公开(公告)日：2004-01-06

申请号：US09989066

申请日：2001-11-21

申请人： Alexander Noam Teutsch ,  Zbigniew Jan Lata ,  David John Baldwin ,  Ross E. Teggatz

发明人： Alexander Noam Teutsch ,  Zbigniew Jan Lata ,  David John Baldwin ,  Ross E. Teggatz

IPC分类号： F21V704

CPC分类号： H01L27/0255 ,  H02H11/003

摘要： The present invention relates to a reverse bias protection structure which comprises a PMOS transistor structure having a drain portion, a gate portion, a source portion and a backgate portion, wherein the gate portion is coupled to a first voltage potential, the source portion is selectively coupleable to a power supply, and the drain portion is selectively coupleable to a circuit needing power to be supplied thereto from the power supply. The reverse bias protection structure further comprises a Schottky diode structure having an anode coupled to the source portion of the PMOS transistor structure, and a cathode coupled to the backgate portion of the PMOS structure. Under forward bias conditions, the PMOS transistor conducts and exhibits a small voltage drop thereacross. Under reverse bias conditions, the PMOS transistor is off and the Schottky structure is reverse biased, thus preventing current through the protection structure.

摘要翻译： 本发明涉及一种反偏置保护结构，其包括具有漏极部分，栅极部分，源极部分和后栅极部分的PMOS晶体管结构，其中栅极部分耦合到第一电压电位，源极部分选择性地 可与电源连接，并且漏极部分选择性地耦合到需要从电源供给的电力的电路。 反向偏置保护结构还包括具有耦合到PMOS晶体管结构的源极部分的阳极的肖特基二极管结构以及耦合到PMOS结构的背栅极部分的阴极。 在正向偏置条件下，PMOS晶体管导通并呈现出小的电压降。 在反向偏置条件下，PMOS晶体管截止，肖特基结构反向偏置，从而防止电流通过保护结构。

公开(公告)号：US06650093B1

公开(公告)日：2003-11-18

申请号：US10162113

申请日：2002-06-03

申请人： Dave Baldwin ,  Sanmukh Patel ,  Ross E. Teggatz

发明人： Dave Baldwin ,  Sanmukh Patel ,  Ross E. Teggatz

IPC分类号： G05F1613

CPC分类号： G05F1/613

摘要： The regulator circuit with an auxiliary boundary regulator that provides enhanced transient response includes: an upper comparator 24 having a first input coupled to a feedback node and a second input coupled to a first reference voltage node V_HIGH; a lower comparator 26 having a first input coupled to the feedback node and a second input coupled to a second reference voltage node V_LOW; a first switching device 30 having a control node coupled to an output of the upper comparator 24; a second switching device 28 having a control node coupled to an output of the lower comparator 26; an inductor 36 having a first end coupled to the first and second switching devices 28 and 30, and a second end coupled to an output node Vout; and a feedback circuit 32 and 34 coupled between the output node Vout and the feedback node. This circuit provides a precise, quiet, linear regulator that provides a tightly regulated output with a fast regulator working in parallel to ensure that the output voltage stays within an acceptable boundary.

摘要翻译： 具有提供增强的瞬态响应的辅助边界调节器的调节器电路包括：具有耦合到反馈节点的第一输入和耦合到第一参考电压节点V_HIGH的第二输入的上比较器24; 下比较器26具有耦合到反馈节点的第一输入和耦合到第二参考电压节点V_LOW的第二输入; 具有耦合到上比较器24的输出的控制节点的第一开关装置30; 具有耦合到下比较器26的输出的控制节点的第二开关装置28; 电感器36，其具有耦合到第一和第二开关器件28和30的第一端，以及耦合到输出节点Vout的第二端; 以及耦合在输出节点Vout和反馈节点之间的反馈电路32和34。 该电路提供了一个精确，安静的线性稳压器，提供紧密调节的输出，并具有并联工作的快速调节器，以确保输出电压保持在可接受的边界内。

公开(公告)号：US06324044B1

公开(公告)日：2001-11-27

申请号：US09305571

申请日：1999-05-05

申请人： Ross E. Teggatz ,  Joseph A. Devore ,  Timothy J. Legat ,  Timothy P. Pauletti ,  David J. Baldwin

发明人： Ross E. Teggatz ,  Joseph A. Devore ,  Timothy J. Legat ,  Timothy P. Pauletti ,  David J. Baldwin

IPC分类号： H02H100

CPC分类号： G06F13/385

摘要： A controlled area network (CAN) driver provides improved symmetry between its differential output signals CAN-H and CAN-L, and provides protection for its low voltage devices from voltage transients occurring on its output lines. A plurality of CAN drivers 80 are serially interconnected to form a driver system, wherein each downstream driver stage receives a time-delayed form of the digital input signal TxD, each stage providing a time-delayed contribution to the differential output signals of the overall driver system.

摘要翻译： 控制区域网络（CAN）驱动器在其差分输出信号CAN-H和CAN-L之间提供改进的对称性，并为其低压器件提供对其输出线路上发生的电压瞬变的保护。 多个CAN驱动器80串联互连以形成驱动器系统，其中每个下游驱动器级接收时间延迟形式的数字输入信号TxD，每个级为整个驱动器的差分输出信号提供时间延迟的贡献 系统。

公开(公告)号：US5801091A

公开(公告)日：1998-09-01

申请号：US903970

申请日：1997-07-31

申请人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

发明人： Taylor R. Efland ,  Satwinder Malhi ,  Michael C. Smayling ,  Joseph A. Devore ,  Ross E. Teggatz ,  Alec J. Morton

IPC分类号： H01L23/482 ,  H01L23/528 ,  H01L29/417 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L23/5286 ,  H01L23/4824 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002

摘要： The device has a semiconductor chip having active circuitry in the face thereof. The circuitry has busing over it containing two conductive layers having a plurality of contacts and vias with spacings between them that alternate with respect to one another to provide current ballasting and improved switching uniformity. The spacings between the alternating contacts and vias provide regions of maximum conductor thickness and therefore reduces the busing resistance. Staggering the rows of alternating contacts and vias provides further current ballasting. A first conducting layer is used to contact and provide electrically isolated low resistive conducting paths to the various semiconductor regions while the second conducting region is used to provide selective contact to the first conductive layer, thus providing a means of busing large currents over active semiconductor area without sacrificing performance parameters.

摘要翻译： 该器件具有在其表面上具有有源电路的半导体芯片。 该电路具有引线，其中包含两个具有多个触点的导电层和在它们之间具有相互间交替的间隙的通孔，以提供电流镇流和改善的开关均匀性。 交替触点和通孔之间的间距提供最大导体厚度的区域，因此降低了阻抗。 交错的交替触点和通孔的排列提供了进一步的电流镇流。 第一导电层用于接触并提供到各种半导体区域的电隔离的低电阻导电路径，而第二导电区域用于提供与第一导电层的选择性接触，从而提供在有源半导体区域上引入大电流的装置 而不牺牲性能参数。

公开(公告)号：US5786724A

公开(公告)日：1998-07-28

申请号：US768876

申请日：1996-12-17

申请人： Ross E. Teggatz

发明人： Ross E. Teggatz

IPC分类号： H03K5/003

CPC分类号： H03K5/003

摘要： A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M.sub.1, M.sub.2, M.sub.3 connected in parallel for respectively driving a capacitive load C.sub.L with a selected different voltage level V.sub.1, V.sub.2 or V.sub.3. Transistors M.sub.1, M.sub.2, M.sub.3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V.sub.1, V.sub.2 or V.sub.3 to charge the load CL. The largest voltage transistor M.sub.3 has its body connected to its source. The lower voltage transistors M.sub.1, M.sub.2 have their bodies respectively connected to switches S.sub.1, S.sub.2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V.sub.3 when the transistors are placed in the OFF condition.

摘要翻译： 电压电平移动电路（图4）具有并联连接的多个PMOS晶体管M1，M2，M3，分别驱动具有所选择的不同电压电平V1，V2或V3的电容性负载CL。 控制晶体管M1，M2，M3，使其中的一个被置于ON状态，其他的处于OFF状态，以连接电压V1，V2或V3中的一个来对负载CL充电。 最大的电压晶体管M3的主体连接到其源极。 低电压晶体管M1，M2的主体分别连接到开关S1，S2，开关S1，S2将晶体管置于ON状态时将主体连接到源极，并将晶体管放置在 OFF状态。

公开(公告)号：US5541799A

公开(公告)日：1996-07-30

申请号：US265609

申请日：1994-06-24

申请人： Thomas A. Schmidt ,  Ross E. Teggatz ,  Joseph A. Devore

发明人： Thomas A. Schmidt ,  Ross E. Teggatz ,  Joseph A. Devore

IPC分类号： H03K17/082 ,  H02H7/10

CPC分类号： H03K17/0822

摘要： In accordance with the present invention, an output current limit circuit for protecting a power MOS output device of an integrated circuit from an excessive drain current comprises a power MOS device 110, a means 30 to sense a predetermined trigger current, and a means 20 to reduce a gate-source voltage on MOS output device 110 to a predetermined approximately fixed value. A drain current I.sub.D flows through power MOS device 110 from output terminal 102 in response to the gate-source voltage. A short circuit condition may allow an excessive amount of drain current I.sub.D to flow through output terminal 102. The gate-source voltage is reduced in response to sensing the trigger current. Reducing the gate-source voltage raises a drain-source resistance of MOS device 110 and reduces drain current I.sub.D so that MOS device 110 is not damaged by the short circuit condition.

摘要翻译： 根据本发明，用于保护集成电路的功率MOS输出装置与过剩漏极电流的输出限流电路包括功率MOS器件110，感测预定触发电流的装置30和装置20至 将MOS输出装置110上的栅极 - 源极电压降低到预定的大致固定值。 漏极电流ID响应于栅极 - 源极电压从输出端子102流过功率MOS器件110。 短路状态可允许过量的漏极电流ID流过输出端子102.响应于感测触发电流，栅极 - 源极电压被降低。 降低栅极 - 源极电压会提高MOS器件110的漏极 - 源极电阻并且减少漏极电流ID，使得MOS器件110不会被短路状态损坏。