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71.发明授权Automatically extensible addressing for shared array built-in self-test (ABIST) circuitry 有权用于共享阵列内置自检（ABIST）电路的自动扩展寻址公开(公告)号：US07757141B2
公开(公告)日：2010-07-13
申请号：US12055595
申请日：2008-03-26
IPC分类号： G01R31/28
CPC分类号： G01R31/3187 , G01R31/31722
摘要： A method for testing integrated circuits (ICs) by automatically extending addressing for shared array built-in self-test (BIST) circuitry, includes polling a plurality of memories to determine which of the plurality of memories are sharing a first comparison tree and mapping a shared array BIST address space to each of the plurality of memories using the first comparison tree. Additionally, the method includes estimating a shared array BIST completion time corresponding to a most significant bits of a maximum total memory address size under test, reconfiguring the shared array BIST circuitry to accommodate the estimated shared array BIST completion time and testing the plurality of memories sharing the first comparison tree.
摘要翻译： 一种用于通过自动扩展用于共享阵列内置自检（BIST）电路的寻址来测试集成电路（IC）的方法，包括轮询多个存储器以确定多个存储器中的哪个存储器共享第一比较树并映射 使用第一比较树将共享阵列BIST地址空间分配给多个存储器中的每一个。 另外，该方法包括估计对应于被测试的最大总存储器地址大小的最高有效位的共享阵列BIST完成时间，重新配置共享阵列BIST电路以适应估计的共享阵列BIST完成时间并测试多个存储器共享 第一个比较树。
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72.发明申请METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK 有权设计多状态恢复电路以将状态恢复到功率管理的功能块的方法公开(公告)号：US20090307637A1
公开(公告)日：2009-12-10
申请号：US12135250
申请日：2008-06-09
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F2217/72
摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.
摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。
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73.发明授权System and method for performing high speed memory diagnostics via built-in-self-test 有权通过内置自检进行高速存储器诊断的系统和方法公开(公告)号：US07607060B2
公开(公告)日：2009-10-20
申请号：US11531035
申请日：2006-09-12
CPC分类号： G11C29/44 , G11C2029/3202
摘要： A system and method for performing high speed memory diagnostics via built-in-self-test (BIST). A test system includes a tester for testing an integrated circuit that includes a BIST circuit and a test control circuit. The BIST circuit further includes a BIST engine and fail logic for testing an imbedded memory array. The test control circuit includes three binary up/down counters, a variable delay, and a comparator circuit. A method includes presetting the counters of the test control circuit, presetting the variable delay to a value that is equal to the latency of the fail logic, setting the BIST cycle counter to decrement mode, presetting the variable delay to zero, re-executing the test algorithm, performing a second test operation of capturing the fail data, and performing a third test operation of transmitting the fail data to the tester.
摘要翻译： 一种用于通过内置自检（BIST）执行高速存储器诊断的系统和方法。 测试系统包括用于测试包括BIST电路和测试控制电路的集成电路的测试器。 BIST电路还包括用于测试嵌入式存储器阵列的BIST引擎和故障逻辑。 测试控制电路包括三个二进制向上/向下计数器，可变延迟和比较器电路。 一种方法包括预设测试控制电路的计数器，将可变延迟预设为等于故障逻辑等待时间的值，将BIST周期计数器设置为递减模式，将可变延迟预置为零，重新执行 测试算法，执行捕获故障数据的第二测试操作，以及执行将失败数据发送给测试者的第三测试操作。
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公开(公告)号：US20090251169A1
公开(公告)日：2009-10-08
申请号：US12099382
申请日：2008-04-08
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/018585 , H03K19/018557 , H03K19/018592
摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.
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公开(公告)号：US20090154269A1
公开(公告)日：2009-06-18
申请号：US11954479
申请日：2007-12-12
CPC分类号： G11C7/20 , G11C5/14 , G11C29/83 , G11C2029/4402
摘要： An approach that manages redundant memory in a voltage island is described. In one embodiment there is a design structure embodied in a machine readable medium used in a design process of a semiconductor device. In this embodiment, the design structure includes one or more voltage islands representing a power cycled region. Each of the one or more voltage islands comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. One or more non-power cycled regions are located about the one or more voltage islands. Each of the one or more non-power cycled regions comprises at least one memory using redundancy and a repair register associated with each memory using redundancy. A redundancy initialization component is coupled to the one or more voltage islands and the one or more non-power cycled regions. The redundancy initialization component is configured to initialize each memory using redundancy and associated repair register with repair data. The redundancy initialization component is configured to initialize a memory using redundancy and associated repair register with repair data independent of, or in conjunction with, the initialization of other memories using redundancy and associated repair registers.
摘要翻译： 描述了管理电压岛中的冗余存储器的方法。 在一个实施例中，存在体现在用于半导体器件的设计过程中的机器可读介质中的设计结构。 在该实施例中，设计结构包括代表功率循环区域的一个或多个电压岛。 一个或多个电压岛中的每一个包括使用冗余的至少一个存储器和使用冗余与每个存储器相关联的修复寄存器。 一个或多个非功率循环区域位于一个或多个电压岛周围。 一个或多个非功率循环区域中的每一个包括使用冗余的至少一个存储器和与使用冗余的每个存储器相关联的修复寄存器。 冗余初始化组件耦合到一个或多个电压岛和一个或多个非功率循环区域。 冗余初始化组件被配置为使用具有修复数据的冗余和相关联的修复寄存器来初始化每个存储器。 冗余初始化组件被配置为使用冗余和相关联的修复寄存器来初始化存储器，其中修复数据与使用冗余和相关联的修复寄存器的其他存储器的初始化无关或与其一起使用。
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公开(公告)号：US07174486B2
公开(公告)日：2007-02-06
申请号：US10303444
申请日：2002-11-22
IPC分类号： G11C29/00
CPC分类号： G11C29/802 , H03K19/1735
摘要： A method and system for repairing defective memory in a semiconductor chip. The chip has memory locations, redundant memory, and a central location for ordered fuses. The ordered fuses identify in compressed format defective sections of the memory locations. The defective sections are replaceable by sections of the redundant memory. The ordered fuses have an associated a fuse bit pattern of bits which sequentially represents the defective sections in the compressed format. The method and system determines the order in which the memory locations are wired together; designs a shift register of latches through the memory locations in accordance with the order in which the memory locations are wired together; and associates each of the latches with a corresponding bit of an uncompressed bit pattern from which the fuse bit pattern is derived. The uncompressed bit pattern comprises a sequence of bits, representing the defective sections in uncompressed format.
摘要翻译： 一种用于修复半导体芯片中的缺陷存储器的方法和系统。 该芯片具有存储器位置，冗余存储器和用于有序保险丝的中心位置。 有序保险丝以压缩格式识别存储器位置的缺陷部分。 有缺陷的部分可由冗余存储器的部分替换。 有序保险丝具有相关联的熔丝位模式，其顺序地表示压缩格式的缺陷部分。 方法和系统确定存储器位置连接在一起的顺序; 根据存储器位置连接在一起的顺序，通过存储器位置设计锁存器的移位寄存器; 并且将每个锁存器与从其导出熔丝位模式的未压缩位模式的对应位相关联。 未压缩比特模式包括一个比特序列，表示未压缩格式的缺陷部分。
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公开(公告)号：US07098721B2
公开(公告)日：2006-08-29
申请号：US10711205
申请日：2004-09-01
申请人： Michael R. Ouellette , Larry Wissel
发明人： Michael R. Ouellette , Larry Wissel
IPC分类号： H01H37/76
CPC分类号： G11C29/027 , G11C17/14 , G11C17/16 , G11C17/18 , G11C29/02 , G11C29/50 , H01L2924/0002 , H01L2924/00
摘要： An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.
摘要翻译： 公开了一种用于低电压编程的集成电路的电子熔丝结构，并结合了差分感测方案。 在Vdd执行感测操作时，以大约1.5倍的Vdd执行编程步骤，这限制了由感测操作引起的电子熔断器的电阻变化。 在感测操作期间，门控晶体管模拟保险丝选择晶体管上的电压降，用于完整的熔丝的情况。 还公开了用于表征电子熔断器的电阻的电路和方法。
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公开(公告)号：US06363023B1
公开(公告)日：2002-03-26
申请号：US09792959
申请日：2001-02-26
IPC分类号： G11C702
摘要： A device and method is provided for reducing power consumption in memory devices. The preferred embodiment reduces power consumption by providing a sense amplifier that reduces power consumption while providing high performance. In the preferred embodiment the sense amplifier comprises a bi-directional sense amp that is configurable for use on low power static random access memory (SRAM) devices. The bi-directional sense amp allows the same sense amp to be used for both read and write operations on the memory cells. The preferred embodiment sense amp facilitates the use of differential data buses, further reducing power consumption while providing high performance. Thus, the preferred embodiment bi-directional differential sense amp reduces the device size and complexity, reducing power consumption while providing high performance memory access.
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79.发明授权公开(公告)号：US06333872B1
公开(公告)日：2001-12-25
申请号：US09707201
申请日：2000-11-06
IPC分类号： G11C700
CPC分类号： G11C29/14
摘要： A structure and method for testing multi-port SRAM cells includes a test controller connected to at least one multi-port SRAM cell (the test controller is adapted to store a pattern into the multi-port SRAM cell and generate a stability test restore clamp), a read/write controller connected to the multi-port SRAM cell (the read/write controller is adapted to simultaneously activate a plurality of wordline ports on the multi-port SRAM cell while the stability test restore clamp is enabled), and a timing control circuit connected to the read/write controller. The timing control circuit is adapted to vary an activation time of the wordline ports. The read/write controller reads from the multi-port SRAM after the stability test restore clamp is deactivated. The read/write controller activates the wordline ports for each multi-port SRAM cell in an array sequentially while all bitlines in the array are held on by the stability test restore clamp. The structure also includes a logic device connected to the test controller adapted to prevent the stability test restore clamp from being enabled unless a test is being performed. The timing control circuit is adapted to be selectively externally controllable to vary the activation time of the wordline ports. The timing control circuit can include a plurality of delay units adapted to be selectively engaged to vary the activation time of the wordline ports. The stability test restore clamp is enabled for at least a wordline pulse.
摘要翻译： 用于测试多端口SRAM单元的结构和方法包括连接到至少一个多端口SRAM单元的测试控制器（测试控制器适于将模式存储到多端口SRAM单元中并产生稳定性测试恢复钳位） ，连接到多端口SRAM单元的读/写控制器（读/写控制器适于同时激活多端口SRAM单元上的多个字线端口，同时稳定性测试恢复钳位被使能），以及定时 控制电路连接到读/写控制器。 定时控制电路适于改变字线端口的激活时间。 在禁用稳定性测试恢复钳位之后，读/写控制器从多端口SRAM读取。 读/写控制器顺序激活阵列中每个多端口SRAM单元的字线端口，同时阵列中的所有位线均由稳定性测试恢复钳位保持。 该结构还包括连接到测试控制器的逻辑设备，其适于防止稳定性测试恢复钳位被启用，除非正在执行测试。 定时控制电路适于选择性地可外部控制以改变字线端口的激活时间。 定时控制电路可以包括适于选择性地接合以改变字线端口的激活时间的多个延迟单元。 稳定性测试恢复钳位使能至少一个字线脉冲。
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公开(公告)号：US20130185684A1
公开(公告)日：2013-07-18
申请号：US13348850
申请日：2012-01-12
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/76 , G06F2217/78
摘要： Disclosed is an integrated circuit design method that determines maximum direct currents for metal components and uses them as design constraints in the design flow in order to avoid/minimize electromigration failures. Short and long metal components are treated differently for purposes of establishing the design constraints. For a short metal component, the maximum direct current as a function of a given temperature for a given expected lifetime of the integrated circuit is determined, another maximum direct current is determined based on the Blech length, and the higher of these two is selected and used as the design constraint for that short metal component. For a long metal component, only the maximum direct current as a function of the given temperature for the given expected lifetime is determined and used as the design constraint. Also disclosed herein are associated system and program storage device embodiments for designing an integrated circuit.
摘要翻译： 公开了集成电路设计方法，其确定金属部件的最大直流电流，并将其用作设计流程中的设计约束，以避免/最小化电迁移故障。 为了建立设计约束的目的，对短和长金属部件进行不同的处理。 对于短金属部件，确定针对集成电路的给定预期寿命的给定温度的函数的最大直流电，基于Blech长度确定另一最大直流电流，并且选择这两个中的较高者， 用作该短金属部件的设计约束。 对于长金属部件，仅确定作为给定预期寿命的给定温度的函数的最大直流电流作为设计约束。 本文还公开了用于设计集成电路的相关联的系统和程序存储设备实施例。
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