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公开(公告)号：US09696995B2
公开(公告)日：2017-07-04
申请号：US12649805
申请日：2009-12-30
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor. Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
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公开(公告)号：US20120191953A1
公开(公告)日：2012-07-26
申请号：US13434903
申请日：2012-03-30
CPC分类号： G06F9/30076 , G06F9/325 , G06F9/3834 , G06F9/3838
摘要： Mechanisms for extracting data dependencies during runtime are provided. With these mechanisms, a portion of code having a loop is executed. A first parallel execution group is generated for the loop, the group comprising a subset of iterations of the loop less than a total number of iterations of the loop. The first parallel execution group is executed by executing each iteration in parallel. Store data for iterations are stored in corresponding store caches of the processor, Dependency checking logic of the processor determines, for each iteration, whether the iteration has a data dependence. Only the store data for stores where there was no data dependence determined are committed to memory.
摘要翻译： 提供了在运行时提取数据依赖关系的机制。 利用这些机制，执行具有循环的一部分代码。 为循环生成第一个并行执行组，该组包括循环的迭代次数小于循环迭代次数的总数。 通过并行执行每个迭代来执行第一个并行执行组。 用于迭代的存储数据存储在处理器的对应存储高速缓存中，处理器的依赖性检查逻辑针对每个迭代确定迭代是否具有数据依赖性。 只有确定了没有数据依赖关系的商店的商店数据被提交到内存。
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73.发明申请Data Parallel Function Call for Determining if Called Routine is Data Parallel 失效数据并行函数调用确定调用例程是否是数据并行的公开(公告)号：US20120180031A1
公开(公告)日：2012-07-12
申请号：US13430168
申请日：2012-03-26
IPC分类号： G06F9/45
CPC分类号： G06F9/30072 , G06F8/456 , G06F9/30189 , G06F9/3851 , G06F9/3887
摘要： Mechanisms for performing data parallel function calls in code during runtime are provided. These mechanisms may operate to execute, in the processor, a portion of code having a data parallel function call to a target portion of code. The mechanisms may further operate to determine, at runtime by the processor, whether the target portion of code is a data parallel portion of code or a scalar portion of code and determine whether the calling code is data parallel code or scalar code. Moreover, the mechanisms may operate to execute the target portion of code based on the determination of whether the target portion of code is a data parallel portion of code or a scalar portion of code, and the determination of whether the calling code is data parallel code or scalar code.
摘要翻译： 提供了在运行期间执行代码中数据并行函数调用的机制。 这些机制可以操作以在处理器中执行具有对目标代码部分的数据并行函数调用的代码的一部分。 这些机制可以进一步操作以在运行时由处理器确定目标代码部分是代码的数据并行部分还是代码的标量部分，并确定调用代码是数据并行代码还是标量代码。 此外，这些机制可以基于代码的目标部分是代码的数据并行部分还是代码的标量部分的确定来执行代码的目标部分，以及确定调用代码是否是数据并行代码 或标量代码。
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74.发明授权Digital thermal sensor test implementation without using main core voltage supply 失效数字热传感器测试实现，不使用主芯电压供应公开(公告)号：US08027798B2
公开(公告)日：2011-09-27
申请号：US11937134
申请日：2007-11-08
CPC分类号： G01K15/00 , G01K15/005
摘要： A method and apparatus are provided for calibrating digital thermal sensors. A processor chip with a plurality of digital thermal sensors receives an analog voltage. A test circuit coupled to the processor chip receives a clock signal and a register coupled to the test circuit outputs a value on each clock cycle to a digital thermal sensor in the plurality of digital thermal sensors. The digital thermal sensor transitions an output state in response to the value of the register received in the digital thermal sensor equaling a temperature threshold of the digital thermal sensor. The value of the register at the point of transition is used to calibrate the digital thermal sensor. An incrementer increments the value of the register on each clock cycle in response to the value of the register received in the digital thermal sensor failing to equal the temperature threshold of the digital thermal sensor.
摘要翻译： 提供了一种用于校准数字热传感器的方法和装置。 具有多个数字热传感器的处理器芯片接收模拟电压。 耦合到处理器芯片的测试电路接收时钟信号，耦合到测试电路的寄存器将每个时钟周期上的值输出到多个数字热传感器中的数字热传感器。 数字热传感器响应于数字热传感器中接收的寄存器的值等于数字热传感器的温度阈值而转换输出状态。 在转换点处的寄存器的值用于校准数字热传感器。 响应于数字热敏传感器接收到的寄存器的值不能等于数字热传感器的温度阈值，增量器会在每个时钟周期内递增寄存器的值。
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75.发明授权公开(公告)号：US07930457B2
公开(公告)日：2011-04-19
申请号：US12361907
申请日：2009-01-29
CPC分类号： G06F13/24
摘要： Mechanisms for communicating with a processor event facility are provided. The mechanisms make use of a channel interface as the primary mechanism for communicating with the processor event facility. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了与处理器事件设施通信的机制。 这些机制使用通道接口作为与处理器事件设施通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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76.发明授权公开(公告)号：US07869459B2
公开(公告)日：2011-01-11
申请号：US12129114
申请日：2008-05-29
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901
摘要： A mechanism for communicating instructions and data between a processor and external devices are provided. The mechanism makes use of a channel interface as the primary mechanism for communicating between the processor and a memory flow controller. The channel interface provides channels for communicating with processor facilities, memory flow control facilities, machine state registers, and external processor interrupt facilities, for example. These channels may be designated as blocking or non-blocking. With blocking channels, when no data is available to be read from the corresponding registers, or there is no space available to write to the corresponding registers, the processor is placed in a low power “stall” state. The processor is automatically awakened, via communication across the blocking channel, when data becomes available or space is freed. Thus, the channels of the present invention permit the processor to stay in a low power state.
摘要翻译： 提供了一种用于在处理器和外部设备之间传送指令和数据的机制。 该机制利用通道接口作为处理器和存储器流控制器之间通信的主要机制。 通道接口例如提供用于与处理器设备，存储器流控制设备，机器状态寄存器和外部处理器中断设备进行通信的通道。 这些通道可以被指定为阻塞或非阻塞。 使用阻塞通道，当没有数据可用于从相应的寄存器读取时，或没有可用空间写入对应的寄存器时，处理器处于低功耗“停止”状态。 当数据可用或空间被释放时，通过阻塞通道的通信自动唤醒处理器。 因此，本发明的通道允许处理器保持在低功率状态。
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公开(公告)号：US20100161848A1
公开(公告)日：2010-06-24
申请号：US12342280
申请日：2008-12-23
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A mechanism for programming a direct memory access engine operating as a single thread processor is provided. A program is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the program located in the local memory is to be executed. The direct memory access engine executes the program without intervention by a host processor. Responsive to the program completing execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.
摘要翻译： 提供了一种用于对作为单线程处理器操作的直接存储器访问引擎进行编程的机制。 从与直接存储器访问引擎相关联的本地存储器中的主处理器接收程序。 在来自主处理器的直接存储器访问引擎中接收到指示将要执行位于本地存储器中的程序的请求。 直接存储器访问引擎在没有主机处理器干预的情况下执行程序。 响应程序完成执行，直接存储器访问引擎向主处理器发送指示程序已经完成执行的完成通知。
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78.发明授权公开(公告)号：US07581067B2
公开(公告)日：2009-08-25
申请号：US11377504
申请日：2006-03-16
申请人： Charles R. Johns
发明人： Charles R. Johns
IPC分类号： G06F12/00
CPC分类号： G06F8/458
摘要： A load when reservation lost instruction for performing cacheline polling is disclosed. Initially, a first process requests an action to be performed by a second process. The request is made via a store operation to a cacheable memory location. The first process then reads the cacheable memory location via a conditional load operation to determine whether or not the requested action has been completed by the second process, and the first process sets a reservation at the cacheable memory location if the requested action has not been completed by the second process. The conditional load operation of the first process is stalled until the reservation at the cacheable memory location has been lost. After the requested action has been completed, the reservation in the cacheable memory location is reset by the second process.
摘要翻译： 公开了用于执行高速缓存行轮询的预约丢失指令时的负载。 最初，第一进程请求通过第二进程执行动作。 该请求通过存储操作进行到可高速缓存的存储器位置。 然后，第一进程通过条件加载操作读取可缓存存储器位置，以确定所请求的动作是否已被第二进程完成，如果所请求的动作尚未完成，则第一进程在可高速缓存的存储器位置设置预留 通过第二个过程。 第一进程的条件加载操作停止，直到可缓存存储器位置的预留已经丢失。 在请求的动作完成之后，可缓存存储器位置中的预留由第二进程复位。
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公开(公告)号：US07535020B2
公开(公告)日：2009-05-19
申请号：US11168591
申请日：2005-06-28
申请人： Munehiro Yoshida , Daniel Stasiak , Michael F. Wang , Charles R. Johns , Hiroki Kihara , Tetsuji Tamura , Kazuaki Yazawa , Iwao Takiguchi
发明人： Munehiro Yoshida , Daniel Stasiak , Michael F. Wang , Charles R. Johns , Hiroki Kihara , Tetsuji Tamura , Kazuaki Yazawa , Iwao Takiguchi
IPC分类号： H01L23/58
CPC分类号： H01L25/162 , G06F1/206 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.
摘要翻译： 用于以集成电路的不同部分提供有用的热测量的方式在集成电路内定位热传感器的系统和方法。 在一个实施例中，集成电路包括多个复制功能块。 单独的热传感器耦合到每个重复功能块，优选地在每个复制功能块上相同的相对位置，并且优选地在热点处。 一个实施例还包括在集成电路中的其它类型的一个或多个功能块上的热传感器。 一个实施例包括位于集成电路芯片的边缘处的冷点处的热传感器。 每个热传感器可以具有端口，以实现传感器和外部组件或设备之间的电源和接地连接或数据连接。
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80.发明申请METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR DISPLAYING IMAGES OF CONFERENCE CALL PARTICIPANTS 有权用于显示会议呼叫参与者的图像的方法，系统和计算机程序产品公开(公告)号：US20080267380A1
公开(公告)日：2008-10-30
申请号：US12172390
申请日：2008-07-14
申请人： Bruce D. D'Amora , Charles R. Johns
发明人： Bruce D. D'Amora , Charles R. Johns
IPC分类号： H04M7/00
CPC分类号： H04N7/152
摘要： The present invention provides a method, system, and computer program product for displaying images of conference call participants. A method in accordance with an embodiment of the present invention includes receiving a call from a user to join a conference call, obtaining a phone number of the user, matching the phone number to a stored graphical representation, and distributing and displaying the matching graphical representation to a predetermined set of users. A voice identification/recognition process can also be used to match the user to a stored graphical representation.
摘要翻译： 本发明提供了一种用于显示电话会议参与者的图像的方法，系统和计算机程序产品。 根据本发明的实施例的方法包括从用户接收加入电话会议的呼叫，获得用户的电话号码，将电话号码与存储的图形表示相匹配，以及分发和显示匹配的图形表示 到预定的一组用户。 语音识别/识别过程也可以用于将用户与存储的图形表示相匹配。
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