公开(公告)号：US20140061786A1

公开(公告)日：2014-03-06

申请号：US13603385

申请日：2012-09-04

申请人： Tsung-Yi Huang ,  Chien-Wei Chiu

发明人： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66681 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes a first conductive type substrate, a second conductive type high voltage well, a first conductive type deep buried region, a field oxide region, a first conductive type body region, a gate, a second conductive type source, and a second conductive type drain. The deep buried region is formed below the high voltage well with a gap in between, and the gap is not less than a predetermined distance.

摘要翻译： 本发明公开了一种双扩散金属氧化物半导体（DMOS）器件及其制造方法。 DMOS器件包括第一导电型衬底，第二导电型高电压阱，第一导电类型深埋入区域，场氧化物区域，第一导电类型体区域，栅极，第二导电型源极和第二导电类型源极 导电型漏极。 深埋区域形成在高压井的下方，间隙为间隙，间隙不小于预定距离。

公开(公告)号：US20140015008A1

公开(公告)日：2014-01-16

申请号：US13549501

申请日：2012-07-15

申请人： Tsung-Yi Huang ,  Jin-Lian Su

发明人： Tsung-Yi Huang ,  Jin-Lian Su

IPC分类号： H01L27/06 ,  H01L21/82

CPC分类号： H01L29/66136 ,  H01L21/265 ,  H01L21/76224 ,  H01L27/0255 ,  H01L27/0814 ,  H01L29/0649

摘要： The present invention discloses a transient voltage suppressor (TVS) circuit, and a diode device therefor and a manufacturing method thereof. The TVS circuit is for coupling to a protected circuit to limit amplitude of a transient voltage which is inputted to the protected circuit. The TVS circuit includes a suppressor device and at least a diode device. The diode device is formed in a substrate, which includes: a well formed in the substrate; a separation region formed beneath the upper surface; a anode region and a cathode region, which are formed at two sides of the separation region beneath the upper surface respectively, wherein the anode region and the cathode region are separated by the separation region; and a buried layer, which is formed in the substrate below the well with a higher impurity density and a same conductive type as the well.

摘要翻译： 本发明公开了一种瞬态电压抑制器（TVS）电路及其二极管装置及其制造方法。 TVS电路用于耦合到受保护电路以限制输入到保护电路的瞬态电压的幅度。 TVS电路包括抑制器装置和至少二极管装置。 二极管器件形成在衬底中，其包括：在衬底中形成的阱; 形成在所述上表面下方的分离区域; 阳极区域和阴极区域，其分别形成在上表面下方的分离区域的两侧，其中阳极区域和阴极区域被分离区域分离; 以及掩埋层，其形成在阱下方的衬底中，具有较高的杂质密度和与该阱相同的导电类型。

公开(公告)号：US08592923B2

公开(公告)日：2013-11-26

申请号：US13280035

申请日：2011-10-24

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/66

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

公开(公告)号：US20130256846A1

公开(公告)日：2013-10-03

申请号：US13864196

申请日：2013-04-16

申请人： Tsung-Yi Huang ,  Chien-Hao Huang ,  Ying-Shiou Lin

发明人： Tsung-Yi Huang ,  Chien-Hao Huang ,  Ying-Shiou Lin

IPC分类号： H01L29/06

CPC分类号： H01L29/06 ,  H01L21/266 ,  H01L29/0688 ,  H01L29/36

摘要： The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

摘要翻译： 本发明公开了半导体重叠PN结构及其制造方法。 该方法包括：提供衬底; 提供第一掩模以限定所述衬底中的P（或N）型阱和至少一个重叠区域; 将P（或N）型杂质注入P（或N）型阱和至少一个重叠区域; 提供具有至少一个开口的第二掩模，以在所述衬底中限定N（或P）型阱，并且在所述至少一个重叠区域中限定至少一个双注入区域; 将N（或P）型杂质注入N（或P）型阱和至少一个双注入区，使得至少一个双注入区具有P型和N型杂质。

公开(公告)号：US20130207185A1

公开(公告)日：2013-08-15

申请号：US13370691

申请日：2012-02-10

申请人： Tsung-Yi Huang ,  Chien-Wei Chiu

发明人： Tsung-Yi Huang ,  Chien-Wei Chiu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/086 ,  H01L29/0611 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66659 ,  H01L29/7835

摘要： An isolated device is formed in a substrate in which is formed a high voltage device. The isolated device includes: an isolated well formed in the substrate by a lithography process and an ion implantation process used in forming the high voltage device; a gate formed on the substrate; a source and a drain, which are located in the isolated well at both sides of the gate respectively; a drift-drain region formed beneath the substrate surface, wherein the gate and the drain are separated by the drift-drain region, and the drain is in the drift-drain region; and a mitigation region, which is formed in the substrate and has a shallowest portion located at least below 90% of a depth of the drift-drain region as measured from the substrate surface, wherein the mitigation region and the drift-drain region are defined by a same lithography process.

摘要翻译： 隔离器件形成在形成高电压器件的衬底中。 隔离装置包括：通过光刻工艺在衬底中形成的隔离阱和用于形成高压器件的离子注入工艺; 形成在基板上的栅极; 源极和漏极分别位于门的两侧的隔离井中; 形成在所述衬底表面下方的漂移漏极区，其中所述栅极和所述漏极由所述漂移 - 漏极区分离，并且所述漏极在所述漂移 - 漏极区中; 以及缓解区域，其形成在所述衬底中，并且具有位于所述衬底表面测量的至少位于所述漂移 - 漏极区域的深度的90％以下的最浅部分，其中所述缓解区域和所述漂移 - 漏极区域被限定 通过相同的光刻工艺。

公开(公告)号：US20130069153A1

公开(公告)日：2013-03-21

申请号：US13235366

申请日：2011-09-17

申请人： Tsung-Yi Huang ,  Chien-Hao Huang

发明人： Tsung-Yi Huang ,  Chien-Hao Huang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7816 ,  H01L21/823418 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/41758 ,  H01L29/423 ,  H01L29/66659 ,  H01L29/7835

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高电压装置包括：具有用于限定器件区域的隔离结构的衬底; 位于所述器件区域中的漂移区域，其中，从顶视图，所述漂移区域包括彼此分离但彼此电连接的多个子区域; 设备区域中的源极和漏极; 以及在衬底的表面上以及器件区域中的源极和漏极之间的栅极。

公开(公告)号：US08377787B2

公开(公告)日：2013-02-19

申请号：US13155957

申请日：2011-06-08

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.

摘要翻译： 提供半导体器件。 在一个实施例中，该器件包括形成在半导体衬底上的衬底和晶体管。 晶体管可以包括栅极结构，源极区和漏极区。 漏极区域包括交替掺杂分布区域。 交变掺杂剖面区域可以包括掺杂剂的高浓度和低浓度的交替区域。 在一个实施例中，晶体管是高压晶体管。

公开(公告)号：US20130020636A1

公开(公告)日：2013-01-24

申请号：US13185951

申请日：2011-07-19

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a well of a substrate. The high voltage device includes: a field oxide region; a gate, which is formed on a surface of the substrate, and part of the gate is located above the field oxide region; a source and a drain, which are formed at two sides of the gate respectively; and a first low concentration doped region, which is formed beneath the gate and has an impurity concentration which is lower than that of the well surrounded, wherein from top view, the first low concentration doped region has an area within the gate and not larger than an area of the gate, and the first low concentration doped region has a depth which is deeper than that of the source and drain.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在衬底的阱中。 高电压装置包括：场氧化物区域; 栅极，其形成在基板的表面上，栅极的一部分位于场氧化物区域的上方; 源极和漏极，分别形成在栅极的两侧; 以及第一低浓度掺杂区，其形成在栅极下方并且具有低于所围绕的阱的杂质浓度，其中从顶视图来看，第一低浓度掺杂区具有栅极内的面积并且不大于 栅极的面积，第一低浓度掺杂区域的深度比源极和漏极深。

公开(公告)号：US08159029B2

公开(公告)日：2012-04-17

申请号：US12256009

申请日：2008-10-22

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US20110309443A1

公开(公告)日：2011-12-22

申请号：US12817413

申请日：2010-06-17

申请人： Tsung-Yi Huang ,  Ying-Shiou Lin

发明人： Tsung-Yi Huang ,  Ying-Shiou Lin

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659

摘要： The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.

摘要翻译： 本发明公开了一种用于控制半导体器件中的杂质浓度分布的方法和由此制成的半导体器件。 控制方法包括以下步骤：提供基板; 限定包括至少一个第一区域的掺杂区域; 通过掩模图案部分地掩蔽所述第一区域; 以及在所述掺杂区域中掺杂杂质以在所述第一区域中形成一个积分掺杂区域，由此所述第一区域的杂质浓度低于所述第一区域未被所述掩模图案掩蔽的情况。