公开(公告)号：US08159029B2

公开(公告)日：2012-04-17

申请号：US12256009

申请日：2008-10-22

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/76

CPC分类号： H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US07816744B2

公开(公告)日：2010-10-19

申请号：US12170133

申请日：2008-07-09

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/49

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US08158475B2

公开(公告)日：2012-04-17

申请号：US12879777

申请日：2010-09-10

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US20110008944A1

公开(公告)日：2011-01-13

申请号：US12879777

申请日：2010-09-10

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US20100006934A1

公开(公告)日：2010-01-14

申请号：US12170133

申请日：2008-07-09

申请人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Puo-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun-Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： A semiconductor structure includes a semiconductor substrate; a first high-voltage well (HVW) region of a first conductivity type overlying the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type overlying the semiconductor substrate and laterally adjoining the first well region; a gate dielectric extending from over the first well region to over the second well region; a drain region in the second well region; a source region on an opposite side of the gate dielectric than the drain region; and a gate electrode on the gate dielectric. The gate electrode includes a first portion directly over the second well region, and a second portion directly over the first well region. The first portion has a first impurity concentration lower than a second impurity concentration of the second portion.

摘要翻译： 半导体结构包括半导体衬底; 覆盖半导体衬底的第一导电类型的第一高电压阱（HVW）区域; 第二导电类型的第二阱区域，与覆盖半导体衬底并横向邻接第一阱区的第一导电类型相反; 栅极电介质，其从所述第一阱区域上延伸到所述第二阱区域上方; 第二阱区中的漏极区; 栅极电介质的与漏极区相反的一侧的源极区; 和栅电极上的栅电极。 栅电极包括直接在第二阱区上的第一部分和直接在第一阱区上的第二部分。 第一部分具有低于第二部分的第二杂质浓度的第一杂质浓度。

公开(公告)号：US08629513B2

公开(公告)日：2014-01-14

申请号：US13007220

申请日：2011-01-14

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/861

摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

摘要翻译： 一种器件包括半导体衬底中的第一和第二重掺杂区域。 绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。 栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。 栅极形成在栅极电介质上。 浮动导体在绝缘区域上方和上方重叠。 金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

公开(公告)号：US20120181629A1

公开(公告)日：2012-07-19

申请号：US13007220

申请日：2011-01-14

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/861

摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

摘要翻译： 一种器件包括半导体衬底中的第一和第二重掺杂区域。 绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。 栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。 栅极形成在栅极电介质上。 浮动导体在绝缘区域上方和上方重叠。 金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

公开(公告)号：US08502326B2

公开(公告)日：2013-08-06

申请号：US12888113

申请日：2010-09-22

申请人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

发明人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

IPC分类号： H01L21/02 ,  H01L21/3205

CPC分类号： H01L21/823462 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.

摘要翻译： 集成电路结构包括半导体衬底和高电压金属氧化物半导体（HVMOS）器件，其包括在半导体衬底中的第一导电类型的第一高电压阱（HVW）区域; 在所述半导体衬底中与所述第一HVW区间隔开的第二导电类型的与所述第一导电类型相反的漏极区; 栅极电介质，其具有直接在所述第一HVW区域上的至少一部分; 以及在栅极电介质上的栅电极。 栅极电介质包括底部栅极氧化物区域; 以及在底部栅极氧化物区域上方的氮化硅区域。

公开(公告)号：US20110133276A1

公开(公告)日：2011-06-09

申请号：US12888113

申请日：2010-09-22

申请人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

发明人： Kong-Beng Thei ,  Jiun-Lei Jerry Yu ,  Chien-Chih Chou ,  Chun-Lin Tsai

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit structure includes a semiconductor substrate and a high-voltage metal-oxide-semiconductor (HVMOS) device, which includes a first high-voltage well (HVW) region of a first conductivity type in the semiconductor substrate; a drain region of a second conductivity type opposite the first conductivity type in the semiconductor substrate and spaced apart from the first HVW region; a gate dielectric with at least a portion directly over the first HVW region; and a gate electrode over the gate dielectric. The gate dielectric includes a bottom gate oxide region; and a silicon nitride region over the bottom gate oxide region.

摘要翻译： 集成电路结构包括半导体衬底和高电压金属氧化物半导体（HVMOS）器件，其包括在半导体衬底中的第一导电类型的第一高电压阱（HVW）区域; 在所述半导体衬底中与所述第一HVW区间隔开的第二导电类型的与所述第一导电类型相反的漏极区; 栅极电介质，其具有直接在所述第一HVW区域上的至少一部分; 以及在栅极电介质上的栅电极。 栅极电介质包括底部栅极氧化物区域; 以及在底部栅极氧化物区域上方的氮化硅区域。

公开(公告)号：US20060205232A1

公开(公告)日：2006-09-14

申请号：US11076702

申请日：2005-03-10

申请人： Lih-Ping Li ,  Tzong-Sheng Chang ,  William Kuo ,  Tsung-Hsien Lee ,  Chun-Lin Tsai ,  Szu-An Wu ,  Yin-Ping Lee

发明人： Lih-Ping Li ,  Tzong-Sheng Chang ,  William Kuo ,  Tsung-Hsien Lee ,  Chun-Lin Tsai ,  Szu-An Wu ,  Yin-Ping Lee

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0276 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828

摘要： A method for etching a dielectric material in a semiconductor device is disclosed. After providing a conductive region, a dielectric layer is formed over the conductive region. A dielectric antireflective coating (DARC) layer is further formed on the dielectric layer. Then, a moisture-removal step is performed that removes moisture from the DARC layer and from an interface region between the dielectric and the DARC layer. A masking pattern is transferred into the DARC layer and the dielectric layer.

摘要翻译： 公开了一种在半导体器件中蚀刻介电材料的方法。 在提供导电区域之后，在导电区域上形成电介质层。 在电介质层上进一步形成电介质抗反射涂层（DARC）层。 然后，进行除湿步骤，其从DARC层和电介质层与DARC层之间的界面区域去除水分。 掩模图案被传送到DARC层和电介质层。