公开(公告)号：US20100177577A1

公开(公告)日：2010-07-15

申请号：US12730994

申请日：2010-03-24

申请人： Chulmin Jung ,  Kang Yong Kim

发明人： Chulmin Jung ,  Kang Yong Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

摘要翻译： 一些实施例包括被配置为接收多个信号的多个节点。 信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。 该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。 传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。 传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。 每个传送路径可以仅包括一个存储元件。 公开了包括附加装置，系统和方法的其它实施例。

公开(公告)号：US07212460B1

公开(公告)日：2007-05-01

申请号：US11294729

申请日：2005-12-05

申请人： Chulmin Jung ,  George Raad

发明人： Chulmin Jung ,  George Raad

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4074 ,  G11C11/4091 ,  G11C2207/065

摘要： A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting. Use of the disclosed circuitry benefits, as one example, the boosting of a DRAM column select line that passes a long distance through the memory array.

摘要翻译： 公开了一种用于沿着电路线升高驱动信号以减少RC延迟的方法和电路。 在一个实施例中，该电路包括一个线路放大器，该线路放大器定位在与电路相距一定距离处，例如跨越存储器阵列驱动信号到线路上。 线路放大器在早期阶段检测线路上的驱动信号，甚至在信号达到其全部电位之前，放大器放大该信号并将其驱动回线路，以帮助提高检测到的信号。 在优选实施例中，放大器包括能够升压两个输入信号线之一的差分放大器。 在替代实施例中，放大器输出可以另外输入到反馈回路，该回路最终驱动上拉晶体管以升高检测到的信号并将其返回到线以进一步辅助差分放大器的升压。 作为一个示例，使用所公开的电路有利于升高通过存储器阵列的长距离的DRAM列选择线。

公开(公告)号：US08896070B2

公开(公告)日：2014-11-25

申请号：US13446462

申请日：2012-04-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L45/00 ,  H01L27/24 ,  H01L27/22 ,  H01L43/08 ,  H01L27/10

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明一般涉及用于垂直堆叠的半导体元件的具有嵌入式（底侧）控制线的装置。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US08289804B2

公开(公告)日：2012-10-16

申请号：US13100967

申请日：2011-05-04

申请人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

发明人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.

摘要翻译： 用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。 根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。 耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压 并且向剩余的2N-1个输出线同时施加第二电压。

公开(公告)号：US20110205830A1

公开(公告)日：2011-08-25

申请号：US13100967

申请日：2011-05-04

申请人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

发明人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

IPC分类号： G11C8/10

CPC分类号： G11C8/10

摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N−1 output lines.

摘要翻译： 用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。 根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。 耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压 并且向剩余的2N-1个输出线同时施加第二电压。

公开(公告)号：US07969812B2

公开(公告)日：2011-06-28

申请号：US12502219

申请日：2009-07-13

申请人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

发明人： Chulmin Jung ,  Dadi Setiadi ,  YoungPil Kim ,  Harry Hongyue Liu ,  Hyung-Kyu Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/10

摘要： Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2N output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2N-1 output lines.

摘要翻译： 用于解码诸如固态存储器（SSM）的半导体器件中的控制线的地址的装置和方法。 根据一些实施例，开关电路包括耦合到2N个输出线和M个输入线的开关器件阵列，其中M和N分别是非零整数，并且每个输出线具有唯一的N位地址。 耦合到开关电路的解码器电路将所选择的输出线的N位地址划分为多个多位子组地址，并且相对于所述子组地址的各个位值断言M个输入线，以施加第一电压 并且向剩余的2N-1个输出线同时施加第二电压。

公开(公告)号：US07894286B2

公开(公告)日：2011-02-22

申请号：US12573750

申请日：2009-10-05

申请人： Chulmin Jung ,  Tae Kim

发明人： Chulmin Jung ,  Tae Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

摘要翻译： 描述了具有减小的增益的放大器级的读出放大器。 读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。 读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。 具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。 具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。 读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。

公开(公告)号：US20110006377A1

公开(公告)日：2011-01-13

申请号：US12502178

申请日：2009-07-13

申请人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

发明人： Hyung-Kyu Lee ,  YoungPil Kim ,  Peter Nicholas Manos ,  Maroun Khoury ,  Dadi Setiadi ,  Chulmin Jung ,  Hsing-Kuen Liou ,  Paramasiyan Kamatchi Subramanian ,  Yongchul Ahn ,  Jinyoung Kim ,  Antoine Khoueir

IPC分类号： H01L27/105 ,  H01L21/18

CPC分类号： H01L27/101 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463 ,  H01L43/08 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1675

摘要： Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.

摘要翻译： 本发明的各种实施例通常涉及一种用于垂直堆叠的半导体元件的嵌入式（底侧）控制线的设备及其形成方法。 根据各种实施例，第一半导体晶片设置有第一面对表面，其上形成有第一导电层。 第一半导体晶片被附接到第二半导体晶片以形成多晶片结构，第二半导体晶片具有形成第二导电晶片的第二相对表面。 所述第一导电层与所述第二导电层接触地接合以在所述结构内形成嵌入的组合导电层。 去除组合导电层的部分以形成多个间隔开的控制线，其以选定的长度或宽度尺寸延伸穿过所述结构。

公开(公告)号：US07701782B2

公开(公告)日：2010-04-20

申请号：US11854933

申请日：2007-09-13

申请人： Chulmin Jung ,  Kang Yong Kim

发明人： Chulmin Jung ,  Kang Yong Kim

IPC分类号： G11C11/34

CPC分类号： G11C7/1006 ,  G11C7/103 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

摘要： Some embodiments include a number of nodes configured to receive a number of signals. The signals may represent information stored in a number of memory cells of a device such as a memory device. The device may include a number of transfer paths having storage elements coupled between the nodes and an output node. The transfer paths may be configured to transfer a selected signal of the signals from one of the nodes to the output node via one of the transfer paths. The transfer paths may be configured to hold a value of the selected signal in only one of the storage elements. Each of the transfer paths may include only one of the storage elements. Other embodiments including additional apparatus, systems, and methods are disclosed.

摘要翻译： 一些实施例包括被配置为接收多个信号的多个节点。 信号可以表示存储在诸如存储器装置的装置的多个存储单元中的信息。 该设备可以包括多个传输路径，其具有耦合在节点和输出节点之间的存储元件。 传输路径可以被配置为经由传输路径之一将信号的选定信号从节点之一传送到输出节点。 传送路径可以被配置为仅将所选信号的值保存在仅一个存储元件中。 每个传送路径可以仅包括一个存储元件。 公开了包括附加装置，系统和方法的其它实施例。

公开(公告)号：US07606097B2

公开(公告)日：2009-10-20

申请号：US11646735

申请日：2006-12-27

申请人： Chulmin Jung ,  Tae Kim

发明人： Chulmin Jung ,  Tae Kim

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on one of the I/O nodes. The first amplifier stage, having a first conductivity-type, amplifies one of the I/O node towards a first voltage. The second amplifier stage, having a second conductivity-type, amplifies the other I/O node towards a second voltage. The sense amplifier also includes a resistance circuit coupled to the second amplifier stage to reduce the gain of the second amplifier stage thereby reducing the rate of amplification of the signal on the corresponding I/O node.

摘要翻译： 描述了具有减小的增益的放大器级的读出放大器。 读出放大器包括第一输入/输出（“I / O”）节点和第二互补I / O节点。 读出放大器包括两个放大器级，每个用于放大I / O节点之一上的信号。 具有第一导电类型的第一放大器级将第一电压的I / O节点之一放大。 具有第二导电类型的第二放大器级将第二电压放大到另一个I / O节点。 读出放大器还包括耦合到第二放大器级的电阻电路，以减小第二放大器级的增益，从而降低相应I / O节点上的信号的放大率。