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103 条记录 (耗时 0.032 秒)

    Power-aware RAM processing
    72.
    发明授权
    Power-aware RAM processing 有权
    电源感知RAM处理

    公开(公告)号：US07877555B1

    公开(公告)日：2011-01-25

    申请号：US11510018

    申请日：2006-08-24

    申请人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

    发明人： Russell George Tessier ,  Vaughn Betz ,  Thiagaraja Golpalsamy ,  David Neto

    IPC分类号： G06F12/00

    CPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C2207/2227

    摘要： Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

    摘要翻译： 逻辑存储器和设计中指定的其他逻辑功能被映射到使用物理存储器和其他设备资源的功率优化实现。 逻辑存储器可以自动映射到许多潜在的物理实现。 对每个潜在的物理实现估计功耗，以选择在功耗和任何其他设计限制方面提供最佳性能的物理实现。 当未访问嵌入式存储器时，潜在的物理实现可以通过时钟使能输入来抑制时钟转换。 读使能和写使能信号可以转换为功能等效的时钟使能信号。 可以创建时钟使能信号，以禁用未使用的存储器访问端口，并在不保养条件期间停用嵌入式存储器块。 潜在的物理实现可以将逻辑存储器分解成两个或多个嵌入式存储器块，以最小化功耗。

    Power-driven timing analysis and placement for programmable logic
    73.
    发明授权
    Power-driven timing analysis and placement for programmable logic 有权
    用于可编程逻辑的功率驱动时序分析和放置

    公开(公告)号：US07861190B1

    公开(公告)日：2010-12-28

    申请号：US10907049

    申请日：2005-03-17

    申请人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    发明人： Yaron Kretchmer ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  Y02T10/82

    摘要： An integrated circuit is divided into two or more different regions, each region being a different voltage domain. In each of the regions, a voltage drop and its impact on performance will be quantified. A place and route engine (or another tool of a computer-aided design flow) will then take these timing considerations into account while performing partitioning of the device. A user's logic design is implemented into the logic array blocks taking into a voltage drop seen at those logic array blocks. Faster paths of the logic design are placed into faster logic array blocks, such as those in a core region of the integrated circuit.

    摘要翻译： 集成电路被分为两个或更多个不同的区域，每个区域是不同的电压域。 在每个区域，电压降及其对性能的影响将被量化。 然后，在执行设备分区时，会考虑到这些时间考虑因素，地方和路线引擎（或计算机辅助设计流程的另一个工具）将考虑这些时间考虑因素。 用户的逻辑设计被实现为在这些逻辑阵列块处看到的电压降的逻辑阵列块中。 将逻辑设计的更快的路径放置在更快的逻辑阵列块中，例如集成电路的核心区域中的那些。

    Periphery clock distribution network for a programmable logic device
    74.
    发明授权
    Periphery clock distribution network for a programmable logic device 有权
    用于可编程逻辑器件的周边时钟分配网络

    公开(公告)号：US07737751B1

    公开(公告)日：2010-06-15

    申请号：US11668521

    申请日：2007-01-30

    申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz

    发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz

    IPC分类号： H03K3/013

    CPC分类号： G06F1/10

    摘要： A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.

    摘要翻译： 可编程逻辑器件（PLD）包括与PLD的高质量，低偏移时钟分配网络分离的信号分配网络，用于从PLD的外围输入/输出区域分配时钟型信号。 信号分配网络包括位于一组外围输入/输出区域附近的中央周边时钟总线，用于将这些区域的时钟信号传导到PLD的时钟脊上。 时钟脊可以专用于信号分配网络，或者可以是覆盖全部或部分PLD的高质量，低偏移时钟分配网络的一部分。 信号分配网络允许比这种高质量的低偏移时钟分配网络更大的偏斜，但是仍然具有比一般的可编程互连和路由资源更高的质量，并且允许较少的偏移。

    Efficient delay elements
    75.
    发明授权
    Efficient delay elements 有权
    高效延时元件

    公开(公告)号：US07629825B1

    公开(公告)日：2009-12-08

    申请号：US11549427

    申请日：2006-10-13

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： H03H11/26

    CPC分类号： H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

    摘要： Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

    摘要翻译： 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

    Systems and methods for reducing static and total power consumption in a programmable logic device
    78.
    发明授权
    Systems and methods for reducing static and total power consumption in a programmable logic device 有权
    用于减少可编程逻辑器件中的静态和总功耗的系统和方法

    公开(公告)号：US07188266B1

    公开(公告)日：2007-03-06

    申请号：US10796501

    申请日：2004-03-08

    申请人： David Mendel ,  Vaughn Betz

    发明人： David Mendel ,  Vaughn Betz

    IPC分类号： G06F1/26 ,  G06F1/32 ,  H03K19/173

    CPC分类号： G06F1/32

    摘要： A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, and period following routing of the programmable logic device.

    摘要翻译： 提供了一种用于降低可编程逻辑器件（PLD）中功耗的方法和系统。 在可编程逻辑器件的技术映射，路由和后续周期期间，优选地可以连续地考虑功率消耗作为电路设计中的一个因素来降低功耗。

    Variable delay circuitry
    79.
    发明授权
    Variable delay circuitry 有权
    可变延迟电路

    公开(公告)号：US07138844B2

    公开(公告)日：2006-11-21

    申请号：US11083482

    申请日：2005-03-18

    申请人： Andy L. Lee ,  Gary Lai ,  Changsong Zhang ,  Vaughn Betz ,  Ryan Fung

    发明人： Andy L. Lee ,  Gary Lai ,  Changsong Zhang ,  Vaughn Betz ,  Ryan Fung

    IPC分类号： H03H11/26

    CPC分类号： H03K5/133 ,  H03K2005/00058

    摘要： Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.

    摘要翻译： 用于向集成电路上的其它电路提供输入数据信号的电路包括一个课程延迟链和一个精细延迟链。 如果需要，这两个延迟链是可级联的，以提供可以通过使用精细延迟链精细分级的可能的延迟量的非常宽的范围。

    Automatic adjustment of optimization effort in configuring programmable devices
    80.
    发明申请
    Automatic adjustment of optimization effort in configuring programmable devices 有权
    自动调整配置可编程设备的优化工作

    公开(公告)号：US20060225021A1

    公开(公告)日：2006-10-05

    申请号：US11097592

    申请日：2005-04-01

    申请人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    发明人： Ketan Padalia ,  Jason Peters ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5054

    摘要： User designs are assigned to a category for each design goal associated with the user design. Each category represents the difficulty of satisfying a design goal. Optimization phases are tailored to different combinations of categories and are selected according to the categories assigned to the user design. A ranking of the relative difficulty of the design goals is determined from the categories associated with the user design. Parameters of an optimization phase can be modified in accordance with this ranking to focus optimization efforts on specific design goals. The parameters may be weights of a cost function used by the optimization phase to evaluate alternative configurations of the user design. The user design can be re-classified into an additional category if the results of the optimization phase do not satisfy design goals, and additional optimization phases are selected based on this re-classification to further optimize the user design.

    摘要翻译： 用户设计被分配到与用户设计相关联的每个设计目标的类别。 每个类别代表满足设计目标的难度。 优化阶段根据类别的不同组合进行调整，并根据分配给用户设计的类别进行选择。 根据与用户设计相关的类别确定设计目标相对难度的排名。 优化阶段的参数可以根据这个排名进行修改，将优化工作集中在具体的设计目标上。 参数可以是优化阶段用于评估用户设计的替代配置的成本函数的权重。 如果优化阶段的结果不满足设计目标，则可以将用户设计重新分类为另外的类别，并且基于该重新分类来选择额外的优化阶段以进一步优化用户设计。