公开(公告)号：US06434710B1

公开(公告)日：2002-08-13

申请号：US09337522

申请日：1999-06-22

申请人： Kiyoko Sato ,  Toshio Shirakihara ,  Tatsunori Kanai ,  Hideaki Hirayama

发明人： Kiyoko Sato ,  Toshio Shirakihara ,  Tatsunori Kanai ,  Hideaki Hirayama

IPC分类号： G06F1107

CPC分类号： G06F11/1474

摘要： A commit controlling scheme for a transaction processing in a system utilizing the check point/roll back scheme, which is capable of guaranteeing the reliability of data of the transaction processing even when the transaction processing and the check point/roll back scheme are employed simultaneously, is described. An issuance of an external output for notifying to a user that a transaction has been committed is delayed until after a new check point for the transaction processing process is generated by the fault recovery mechanism at a timing later than a commit of the transaction by the transaction processing process. This can be realized by delaying an issuance of a transaction commit notice from the transaction processing process, or by intercepting a transaction commit notice sent from the transaction processing process, or else by delaying an issuance of the external output by the client process after receiving a transaction commit notice from the transaction processing process.

摘要翻译： 一种使用检查点/回滚方式的系统中的事务处理的提交控制方案，其即使在同时采用事务处理和检查点/回滚方案的情况下也能够保证事务处理的数据的可靠性， 被描述。 发出用于通知用户交易已被提交的外部输出被延迟，直到事务处理过程的新的检查点在故障恢复机制产生之后的时间晚于交易的交易的交易时间 处理过程。 这可以通过延迟来自事务处理过程的事务提交通知的发布，或者通过截取从事务处理过程发送的事务提交通知来实现，或者通过在接收到客户端进程之后延迟由客户端进程发出外部输出 来自事务处理过程的事务提交通知。

公开(公告)号：US06185702B2

公开(公告)日：2001-02-06

申请号：US09012463

申请日：1998-01-23

申请人： Toshio Shirakihara ,  Hideaki Hirayama ,  Kiyoko Sato ,  Tatsunori Kanai

发明人： Toshio Shirakihara ,  Hideaki Hirayama ,  Kiyoko Sato ,  Tatsunori Kanai

IPC分类号： G06F1110

CPC分类号： G06F11/1438

摘要： A process state management scheme capable of acquiring process states consistently even in a case where a new process is generated from some process, while using the synchronous checkpointing method. This scheme prohibits a new process generation during a process state acquisition, which can be realized by judging whether a process generation request by a first process for generating a second process is prior to a process state acquisition request or not, and generating the second process from the first process accordingly. This scheme also prohibits a process state acquisition during a new process generation, which can be realized by acquiring a process state at each of the first and second processes after a notice of the identifier of the second process from the first process is received, when a notice of the identifier of the second process from the second process is prior to the notice from the first process.

摘要翻译： 即使在使用同步检查点方法的情况下，即使在从某个处理生成新处理的情况下，也能够一致地获取处理状态的处理状态管理方案。 该方案禁止在处理状态获取期间的新的处理生成，其可以通过判断通过用于生成第二处理的第一处理的处理生成请求是否在处理状态获取请求之前来实现，并且从第 相应的第一个过程。 该方案还禁止在新进程生成期间的进程状态获取，这可以通过在从第一进程获得第二进程的标识符的通知被接收到之后获取第一和第二进程中的每一个处理状态来实现， 来自第二进程的第二进程的标识符的通知在从第一进程通知之前。

公开(公告)号：US5862403A

公开(公告)日：1999-01-19

申请号：US603759

申请日：1996-02-16

申请人： Tatsunori Kanai ,  Shigehiro Asano ,  Takeshi Aikawa ,  Shinya Amano

发明人： Tatsunori Kanai ,  Shigehiro Asano ,  Takeshi Aikawa ,  Shinya Amano

IPC分类号： G06F3/06 ,  G06F11/10 ,  H04L12/54 ,  H04L12/861 ,  H04L12/883 ,  G06F15/02

CPC分类号： H04L12/5693 ,  G06F11/1076 ,  G06F11/1088 ,  G06F3/0601 ,  H04L49/90 ,  H04L49/9021 ,  H04L49/9047 ,  H04L49/9073 ,  G06F2003/0692

摘要： A continuous data server apparatus incorporating a plurality of buffer memory units for storing the continuous data read out by the data memory control units and to be given to the communication control unit, at least one buffer memory unit being provided dedicatedly for each combination of one data memory control unit group formed by at least one data memory control unit and one communication control unit group formed by at least one communication control unit. The apparatus may further incorporate a plurality of calculation units connected in series, where each calculation unit is connected between corresponding one data memory control unit group and at least one buffer memory unit, and carrying out a prescribed calculation processing. The continuous data can be arranged over a plurality of data memory control units in word units, such that the data memory control units read out the continuous data in block units, the buffer memory units store the continuous data in block units, and the communication control unit transfers the continuous data obtained by reading out data the buffer memory units sequentially in word units.

摘要翻译： 一种连续数据服务器装置，其包括多个缓冲存储器单元，用于存储由数据存储器控制单元读出的连续数据，并被提供给通信控制单元，至少一个缓冲存储器单元专门为一个数据的每个组合提供 由至少一个数据存储器控制单元形成的存储器控​​制单元组和由至少一个通信控制单元形成的一个通信控制单元组。 该装置还可以包括串联连接的多个计算单元，其中每个计算单元连接在相应的一个数据存储器控制单元组和至少一个缓冲存储器单元之间，并执行规定的计算处理。 连续数据可以以单位单位布置在多个数据存储器控制单元上，使得数据存储器控制单元以块为单位读出连续数据，缓冲存储器单元以块为单位存储连续数据，并且通信控制 单元通过以字为单位顺序地读出缓冲存储器单元的数据而获得的连续数据。

公开(公告)号：US09105358B2

公开(公告)日：2015-08-11

申请号：US13157396

申请日：2011-06-10

申请人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada

发明人： Masaya Tarui ,  Tatsunori Kanai ,  Yutaka Yamada

IPC分类号： G06F11/16 ,  G06F11/10 ,  G11C29/04 ,  G11C29/42 ,  G06F11/08 ,  H03M13/19

CPC分类号： G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/08 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1666 ,  G11C29/42 ,  H03M13/19

摘要： In one embodiment, a memory system for writing redundant data output by an encoding processing circuit, comprises a memory, a encoding processing circuit, and a decoding circuit. The memory is electrically rewritable by using memory cells. The memory cells are capable of having two different resistance values corresponding to logical values of 1 or 0 respectively. The redundant data is read from and a predetermined logical value is written to the memory by flowing current in a same direction. The encoding processing circuit performs redundant encoding processing on target data and outputs redundant data. A number of bits having the predetermined logical value exceeds a number of bits having the logical value other than the predetermined logical value, for writing the redundant data to the memory. A decoding circuit reads data from the memory, and performs a decoding process on the data.

摘要翻译： 在一个实施例中，用于写入由编码处理电路输出的冗余数据的存储器系统包括存储器，编码处理电路和解码电路。 存储器通过使用存储器单元进行电可重写。 存储单元能够分别具有对应于逻辑值1或0的两个不同的电阻值。 读取冗余数据，并且通过沿相同方向流动电流将预定的逻辑值写入存储器。 编码处理电路对目标数据进行冗余编码处理，并输出冗余数据。 具有预定逻辑值的位数超过具有除了预定逻辑值之外的逻辑值的比特数，用于将冗余数据写入存储器。 解码电路从存储器读取数据，并对数据进行解码处理。

公开(公告)号：US08892810B2

公开(公告)日：2014-11-18

申请号：US13399185

申请日：2012-02-17

申请人： Hiroto Nakai ,  Tatsunori Kanai ,  Kenichi Maeda

发明人： Hiroto Nakai ,  Tatsunori Kanai ,  Kenichi Maeda

IPC分类号： G06F12/02 ,  G06F9/54

CPC分类号： G06F9/524 ,  G06F9/544 ,  G06F12/0246

摘要： According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.

摘要翻译： 根据一个实施例，半导体器件包括处理器和存储器件。 存储器件具有非易失性半导体存储器件，并且被配置为用作处理器的主存储器。 当处理器执行多个程序时，处理器管理作为各个程序的工作流程执行程序所需的信息，并创建表，其保持各工作组所需的信息和各条信息的地址之间的关系 在存储器件中，用于各个工作台。 处理器参考相应工作台的相应表访问存储器件。

公开(公告)号：US08381072B2

公开(公告)日：2013-02-19

申请号：US13584182

申请日：2012-08-13

申请人： Tatsunori Kanai ,  Yutaka Yamada

发明人： Tatsunori Kanai ,  Yutaka Yamada

IPC分类号： H03M13/00

CPC分类号： G06F11/1064

摘要： A cache memory has a data holding unit having multiple cache lines each of which includes an address area, a data area and a dirty bit, and a controller which is given read data and a correction execution signal indicating whether or not error correction has been performed for the read data, the read data has been read from a memory storing error-correction-coded data, which also stores address information corresponding to the read data into the address area of any one of the multiple cache lines, stores the read data into the data area, and sets a predetermine value as the dirty bit on the basis of the correction execution signal.

摘要翻译： 高速缓冲存储器具有数据保持单元，该数据保持单元具有多个高速缓存线，每条高速缓存行包括地址区，数据区和脏位，以及给予读取数据的控制器和指示是否执行了纠错的校正执行信号 对于读取数据，读取数据已从存储错误校正编码数据的存储器中读出，该数据还将与读取数据相对应的地址信息存储到多个高速缓存行中的任一个的地址区域中，将读取的数据存储到 数据区域，并且基于校正执行信号将预定值设置为脏位。

公开(公告)号：US20120246397A1

公开(公告)日：2012-09-27

申请号：US13491824

申请日：2012-06-08

申请人： Hiroto NAKAI ,  Tatsunori Kanai

发明人： Hiroto NAKAI ,  Tatsunori Kanai

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G06F12/0638

摘要： According to one embodiment, a storage device management device is connected to a random access memory and a first storage device. When the random access memory includes a free region sufficient to store write data, the write data is stored onto the random access memory. Data on the random access memory selected in the descending order of elapsed time from the last access is sequentially copied onto the first storage device, and a region in the random access memory which has stored the copied data is released. When stored on the random access memory, the read data is read from the random access memory to the processor. When stored on the first storage device, the read data is copied onto the random access memory and read from the random access memory to the processor.

摘要翻译： 根据一个实施例，存储设备管理设备连接到随机存取存储器和第一存储设备。 当随机存取存储器包括足以存储写入数据的空闲区域时，写入数据被存储到随机存取存储器中。 按照从最后访问经过的时间的降序选择的随机存取存储器上的数据被顺序复制到第一存储设备上，并且释放存储了复制数据的随机存取存储器中的区域。 当存储在随机存取存储器中时，将读取的数据从随机存取存储器读取到处理器。 当存储在第一存储设备上时，将读取的数据复制到随机存取存储器中并从随机存取存储器读取到处理器。

公开(公告)号：US08166356B2

公开(公告)日：2012-04-24

申请号：US12393251

申请日：2009-02-26

申请人： Tatsunori Kanai

发明人： Tatsunori Kanai

IPC分类号： G06F11/00

CPC分类号： G06F11/1008

摘要： A memory system has a redundancy coding circuit that performs redundancy coding process for write data, an inverter circuit which inverts values of individual bits of the data that has resulted from the redundancy coding process, a selector which selects the data that has resulted from the redundancy coding process or data that has been inverted by the inverter circuit based on a selecting signal, a memory which stores the selected data, a comparator which compares data read from the memory with the selected data and outputs a comparison result, a write control circuit which generates the selecting signal based on the comparison results, and a redundancy decoding circuit that performs a redundancy decoding process for data read from the memory to output the processed data.

摘要翻译： 存储器系统具有对写入数据执行冗余编码处理的冗余编码电路，对从冗余编码处理得到的数据的各位的值进行反转的反相器电路，选择由冗余产生的数据的选择器 编码处理或基于选择信号被逆变器电路反相的数据，存储所选择的数据的存储器，将从存储器读取的数据与所选择的数据进行比较并输出比较结果的比较器，写入控制电路， 基于比较结果生成选择信号，以及冗余解码电路，对从存储器读取的数据进行冗余解码处理，输出处理后的数据。

公开(公告)号：US07877751B2

公开(公告)日：2011-01-25

申请号：US11232984

申请日：2005-09-23

申请人： Seiji Maeda ,  Tatsunori Kanai

发明人： Seiji Maeda ,  Tatsunori Kanai

IPC分类号： G06F9/46 ,  G06F1/00

CPC分类号： G06F9/4893 ,  G06F1/206 ,  G06F1/329 ,  Y02D10/24

摘要： According to an aspect of the present invention, heat emissions of processors are level among the processors, and it is possible to suppress occurrence of stop of process due to overheating. The control IC assigns tasks to the processors, and thereafter rectifies an assignment result such that temperatures of the processors become almost level among the processors, on the basis of the temperatures of the processors obtained by temperature sensors. This structure enables level heat emissions among the processors, and suppresses occurrence of stop of process due to overheating.

摘要翻译： 根据本发明的一个方面，处理器的热排放是处理器之间的水平，并且可以抑制由于过热而导致的处理停止的发生。 控制IC将任务分配给处理器，然后基于由温度传感器获得的处理器的温度，对处理器中的处理器的温度几乎达到一定程度的分配结果进行整流。 这种结构使得处理器之间能够发生热量排放，并且抑制由于过热而导致的过程停止的发生。

公开(公告)号：US07770176B2

公开(公告)日：2010-08-03

申请号：US11233026

申请日：2005-09-23

申请人： Seiji Maeda ,  Tatsunori Kanai

发明人： Seiji Maeda ,  Tatsunori Kanai

IPC分类号： G06F9/46 ,  G06F1/00

CPC分类号： G06F9/4893 ,  G06F1/206 ,  Y02D10/24

摘要： According to an aspect of the present invention, the processor temperatures can be leveled among processors, thereby suppressing the occurrence of stop of processing due to overheating. For example, on the basis of the temperatures of the processors sensed by temperature sensors, the control IC assigns the processor whose temperature is the lowest to the task whose heat emission is the highest. This makes it possible to level the processor temperatures among processors and suppress occurrence of stop of processing due to overheating.

摘要翻译： 根据本发明的一个方面，可以在处理器之间调整处理器温度，从而抑制由于过热而导致的处理停止的发生。 例如，基于由温度传感器感测到的处理器的温度，控制IC将温度最低的处理器分配给发热最高的任务。 这使得可以对处理器之间的处理器温度进行调整，并抑制由于过热而导致的处理停止的发生。