公开(公告)号：US07598577B2

公开(公告)日：2009-10-06

申请号：US10383632

申请日：2003-03-10

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L29/72

CPC分类号： G11C11/155

摘要： A magnetic memory device comprises magneto-resistance elements each including a cylindrical fixed magnetization layer, an insulating film which covers an external surface of the fixed magnetization layer, and a free magnetization layer which faces the fixed magnetization layer through the insulating film and covers a surface of the insulating film, wherein a magnetization direction of the fixed magnetization layer is parallel to a central axis direction of the cylinder.

摘要翻译： 磁存储器件包括磁阻元件，每个磁阻元件包括圆柱形固定磁化层，覆盖固定磁化层外表面的绝缘膜和通过绝缘膜面向固定磁化层并覆盖表面的自由磁化层 ，其中所述固定磁化层的磁化方向平行于所述气缸的中心轴线方向。

公开(公告)号：US07405962B2

公开(公告)日：2008-07-29

申请号：US11482817

申请日：2006-07-10

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： G11C11/00

CPC分类号： G11C11/15 ,  G11C11/1659 ,  G11C2213/71

摘要： MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.

摘要翻译： MTJ元件被累积在半导体衬底上的多个部分中。 用作读取线并沿X方向延伸的第一导电线连接到MTJ元件的引脚层。 用作写入线和读取线并沿X方向延伸的第二导线连接到MTJ元件的自由层。 写行在Y方向上延伸，并与写入行上方和下方的两个MTJ元素共享。 写入线上方和下方的两个MTJ元件与写入线对称。

公开(公告)号：US20060262595A1

公开(公告)日：2006-11-23

申请号：US11482817

申请日：2006-07-10

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： G11C11/00

CPC分类号： G11C11/15 ,  G11C11/1659 ,  G11C2213/71

摘要： MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.

公开(公告)号：US07135735B2

公开(公告)日：2006-11-14

申请号：US10791749

申请日：2004-03-04

申请人： Yoshiaki Fukuzumi ,  Takeshi Kajiyama

发明人： Yoshiaki Fukuzumi ,  Takeshi Kajiyama

IPC分类号： H01L29/76

CPC分类号： H01L21/84 ,  H01L27/108 ,  H01L27/1203 ,  H01L29/7841

摘要： A semiconductor device comprising: a support substrate; an embedded insulating layer formed on the support substrate; a semiconductor layer on the embedded insulating layer; at least an element region formed in the semiconductor layer; a plurality of source/drain regions of a first conductivity type, formed in the element region at predetermined intervals; a plurality of body regions of a second conductivity type, sandwiched between a pair of adjacent ones of the source/drain regions in the element region; and a gate formed on each of the body regions with a gate insulating film being laid between them, each of the source/drain regions including: an inner high-concentration portion extending to the embedded insulating layer, and an outer low-concentration portion surrounding the inner high-concentration portion and having a direct contact with the body regions.

摘要翻译： 一种半导体器件，包括：支撑衬底; 形成在所述支撑基板上的嵌入绝缘层; 嵌入绝缘层上的半导体层; 至少形成在所述半导体层中的元件区域; 多个第一导电类型的源极/漏极区域，以预定间隔形成在元件区域中; 多个第二导电类型的主体区域，被夹在元件区域中的一对相邻源极/漏极区域之间; 以及形成在每个所述主体区域上的栅极，栅极绝缘膜被放置在它们之间，每个所述源极/漏极区域包括：延伸到所述嵌入绝缘层的内部高浓度部分和围绕 内部高浓度部分并且与身体区域直接接触。

公开(公告)号：US20050146955A1

公开(公告)日：2005-07-07

申请号：US10979327

申请日：2004-11-03

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L27/10 ,  G11C11/14 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L27/24 ,  H01L43/08 ,  H01L51/00 ,  H01L51/05

CPC分类号： H01L27/24 ,  B82Y10/00 ,  G11C11/16 ,  H01L27/224 ,  H01L51/0062 ,  H01L51/0078

摘要： A resistance change memory includes a memory element, and a first organic semiconductor layer in contact with the memory element.

摘要翻译： 电阻变化存储器包括存储元件和与存储元件接触的第一有机半导体层。

公开(公告)号：US06861752B2

公开(公告)日：2005-03-01

申请号：US10357357

申请日：2003-02-04

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L21/768 ,  G11C11/16 ,  H01L21/8242 ,  H01L21/8246 ,  H01L23/522 ,  H01L27/00 ,  H01L27/06 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L23/5226 ,  H01L27/0688 ,  H01L27/10882 ,  H01L27/228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a first wiring line having a first through hole, and a first connection member which extends through the first through hole at an interval from the first wiring line.

摘要翻译： 半导体器件包括具有第一通孔的第一布线和从第一布线间隔延伸穿过第一通孔的第一连接构件。

公开(公告)号：US20050002248A1

公开(公告)日：2005-01-06

申请号：US10866129

申请日：2004-06-14

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C7/00

CPC分类号： H01L27/222 ,  B82Y10/00

摘要： A semiconductor memory device includes a semiconductor substrate, and a first magneto resistive element separated from the semiconductor substrate, and including a first magnetic layer and a first nonmagnetic layer. The first magnetic layer and the first nonmagnetic layer are formed in a direction perpendicular to the semiconductor substrate.

公开(公告)号：US06760250B2

公开(公告)日：2004-07-06

申请号：US10306404

申请日：2002-11-29

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： G11C1100

CPC分类号： G11C11/15

摘要： MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. Upper lines and lower lines extending in the X direction are connected to the MTJ elements. The number of MTJ elements arranged in each portion is gradually increased from a lower portion towards an upper portion. With respect to the upper lines, the upper lines arranged in the lower portion are connected to transistors present near an array of the MTJ elements, and the upper lines arranged in the upper portion are connected to transistors distant from the array of the MTJ elements. Also with respect to the lower lines, the lower lines in the lower portion are connected to transistors nearer to the array of the TRM elements than the lower lines in the upper portion.

公开(公告)号：US06653665B2

公开(公告)日：2003-11-25

申请号：US10073338

申请日：2002-02-13

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L2974

CPC分类号： H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/7436

摘要： A semiconductor device according to an aspect of the present invention includes a substrate having a semiconductor substrate and a semiconductor layer provided on the semiconductor substrate, said semiconductor layer being insulated by an insulating film; a thyristor with a gate, its pnpn structure being laterally formed in said semiconductor layer of said substrate; and a transistor formed in said semiconductor layer of said substrate; said transistor being connected to one terminal of said thyristor. A method of manufacturing a semiconductor device according to other aspect of the present invention includes defining an element forming region isolated by an element isolation insulation film in a semiconductor layer of a first conductivity type provided on a semiconductor substrate, said semiconductor layer being insulated by an insulation film provided on the semiconductor substrate; forming a second base region of a first conductivity type in said element forming region; forming a first gate electrode of the thyristor and a second gate of the transistor above said second base region, said first and second gate electrodes being arranged in parallel; implanting ions to form a source and drain diffused regions of the second conductivity at both sides of said second gate electrode, and to form, at the same time, a second emitter region of the second conductivity type and a first base region, one of said source and drain diffused regions and said second emitter region being common region; providing a hole penetrating said first base region and said insulating film under said base region; and filling said hole with material of the first conductivity type to obtain a plug member as a first emitter region which contacts said semiconductor substrate.

摘要翻译： 根据本发明的一个方面的半导体器件包括具有半导体衬底和设置在半导体衬底上的半导体层的衬底，所述半导体层被绝缘膜绝缘; 具有栅极的晶闸管，其pnpn结构横向形成在所述衬底的所述半导体层中; 以及形成在所述衬底的所述半导体层中的晶体管; 所述晶体管连接到所述晶闸管的一个端子。 根据本发明的另一方面的制造半导体器件的方法包括限定由设置在半导体衬底上的第一导电类型的半导体层中的元件隔离绝缘膜隔离的元件形成区域，所述半导体层由 设置在半导体基板上的绝缘膜; 在所述元件形成区域中形成第一导电类型的第二基区; 形成所述晶闸管的第一栅电极和位于所述第二基极区之上的所述晶体管的第二栅极，所述第一和第二栅极平行布置; 注入离子以在所述第二栅电极的两侧形成源极和漏极扩散区域，并且同时形成第二导电类型的第二发射极区域和第一基极区域，所述第一基极区域中的一个 源极和漏极扩散区域和所述第二发射极区域是公共区域; 在所述基底区域提供穿透所述第一基底区域和所述绝缘膜的孔; 以及用所述第一导电类型的材料填充所述孔，以获得作为与所述半导体衬底接触的第一发射极区的插塞构件。

公开(公告)号：US06525360B2

公开(公告)日：2003-02-25

申请号：US09733906

申请日：2000-12-12

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L31119

CPC分类号： H01L21/28123 ,  H01L21/76232 ,  H01L29/4238

摘要： In a MOS transistor using shallow trench isolation, a pattern of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a direction perpendicular to an extension direction of a gate electrode wiring. The pattern of element formation region is constructed as described above, so that an element formation region is formed in a lager current path in a corner device. Thus, a lowering of a threshold voltage (a short channel effect) due to the comer device can be restricted without increasing a width of the gate electrode wiring.

摘要翻译： 在使用浅沟槽隔离的MOS晶体管中，元件形成区域的图案具有六边形的形状，其中六边形沿垂直于栅电极布线的延伸方向的方向被压缩成像菱形的形状。 如上所述构成元件形成区域的图案，使得元件形成区域形成在拐角装置中的较大电流路径中。 因此，可以在不增加栅电极布线的宽度的情况下限制由拐角装置引起的阈值电压（短沟道效应）的降低。