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    Methods of die sawing
    71.
    发明申请
    Methods of die sawing 有权
    模切方法

    公开(公告)号：US20100197114A1

    公开(公告)日：2010-08-05

    申请号：US12798587

    申请日：2010-04-06

    申请人： Shin-Puu Jeng ,  Hao-Yi Tsai

    发明人： Shin-Puu Jeng ,  Hao-Yi Tsai

    IPC分类号： H01L21/78

    CPC分类号： H01L21/78 ,  B28D5/022

    摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.

    摘要翻译： 一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。 每个管芯区域包括形成在衬底上的至少一个第一导电结构。 每个划线区域包括至少一个有效区域和至少一个非有源区域。 有源区包括形成在其中的第二导电结构。 该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

    Laser fuse with efficient heat dissipation
    73.
    发明授权
    Laser fuse with efficient heat dissipation 有权
    激光熔丝具有高效散热

    公开(公告)号：US07397106B2

    公开(公告)日：2008-07-08

    申请号：US11299999

    申请日：2005-12-12

    申请人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

    发明人： Hao-Yi Tsai ,  Chao-Hsiang Yang ,  Shang-Yun Hou ,  Chia-Lun Tsai ,  Shin-Puu Jeng

    IPC分类号： H01L23/62

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure having an efficient thermal path and a method for forming the same are provided. The semiconductor structure includes a protection ring over a semiconductor substrate and substantially encloses a laser fuse structure. The laser fuse structure includes a laser fuse and a connection structure connecting the fuse to integrated circuits. The protection ring is thermally coupled to the semiconductor substrate by contacts. The semiconductor structure further includes a metal plate conducting heat generated by a laser beam to the protection ring.

    摘要翻译： 提供了具有有效的热路径的半导体结构及其形成方法。 半导体结构包括半导体衬底上的保护环，并且基本上包围激光熔丝结构。 激光熔丝结构包括激光熔丝和将熔丝连接到集成电路的连接结构。 保护环通过触点热耦合到半导体衬底。 半导体结构还包括将由激光束产生的热量传导到保护环的金属板。

    METHODS OF DIE SAWING AND STRUCTURES FORMED THEREBY
    74.
    发明申请
    METHODS OF DIE SAWING AND STRUCTURES FORMED THEREBY 有权
    切割方法和形成的结构

    公开(公告)号：US20070293019A1

    公开(公告)日：2007-12-20

    申请号：US11424367

    申请日：2006-06-15

    申请人： Shin-Puu Jeng ,  Hao-Yi Tsai

    发明人： Shin-Puu Jeng ,  Hao-Yi Tsai

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  B28D5/022

    摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.

    摘要翻译： 一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。 每个管芯区域包括形成在衬底上的至少一个第一导电结构。 每个划线区域包括至少一个有效区域和至少一个非有源区域。 有源区包括形成在其中的第二导电结构。 该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

    Methods of die sawing
    75.
    发明授权
    Methods of die sawing 有权
    模切方法

    公开(公告)号：US08058151B2

    公开(公告)日：2011-11-15

    申请号：US12798587

    申请日：2010-04-06

    申请人： Shin-Puu Jeng ,  Hao-Yi Tsai

    发明人： Shin-Puu Jeng ,  Hao-Yi Tsai

    IPC分类号： H01L21/46 ,  H01L21/78 ,  H01L21/301

    CPC分类号： H01L21/78 ,  B28D5/022

    摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.

    摘要翻译： 一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。 每个管芯区域包括形成在衬底上的至少一个第一导电结构。 每个划线区域包括至少一个有源区和至少一个非有源区。 有源区包括形成在其中的第二导电结构。 该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

    Flexible structures for interconnect reliability test
    76.
    发明授权
    Flexible structures for interconnect reliability test 有权
    用于互连可靠性测试的柔性结构

    公开(公告)号：US07776627B2

    公开(公告)日：2010-08-17

    申请号：US11971072

    申请日：2008-01-08

    申请人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu

    发明人： Shin-Puu Jeng ,  Shang-Yun Hou ,  Hao-Yi Tsai ,  Anbiarshy N. F. Wu

    IPC分类号： H01L21/66

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.

    摘要翻译： 一种用于形成集成电路结构的方法包括形成测试晶片。 形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。 第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。 每个连接块单元包括两个连接块和连接两个连接块的金属线。 该方法还包括形成将第一多个单元块彼此分离的多个单元块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

    METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE
    79.
    发明申请
    METHOD FOR FABRICATING AIR GAP FOR SEMICONDUCTOR DEVICE 有权
    用于制造半导体器件的空气隙的方法

    公开(公告)号：US20080076258A1

    公开(公告)日：2008-03-27

    申请号：US11533809

    申请日：2006-09-21

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Shin-Puu Jeng

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7682 ,  H01L21/0206

    摘要： A method for fabricating an interconnect structure in a semiconductor device. A masking layer is formed on a dielectric layer formed on a substrate, having at least one opening. The opening is transferred into the dielectric layer. A Plasma stripping process is performed to remove the masking layer, such that a damaged sidewall portion of the dielectric layer surrounding the opening therein is formed. The opening in the dielectric layer is filled with a conductive element. The damaged sidewall portion of the dielectric layer is removed to form a gap between the dielectric layer and the conductive element, wherein substances from removal of the damaged sidewall portion of the dielectric layer are formed on the conductive element. The substances are removed using a citric acid solution.

    摘要翻译： 一种在半导体器件中制造互连结构的方法。 在形成在基板上的电介质层上形成有至少一个开口的掩模层。 开口转移到电介质层中。 进行等离子体剥离处理以去除掩模层，从而形成围绕其中的开口的电介质层的受损侧壁部分。 电介质层中的开口填充有导电元件。 去除电介质层损坏的侧壁部分，以形成电介质层和导电元件之间的间隙，其中去除导电元件上介质层损坏的侧壁部分的物质。 使用柠檬酸溶液除去物质。

    Semiconductor device structure and methods of manufacturing the same
    80.
    发明申请
    Semiconductor device structure and methods of manufacturing the same 有权
    半导体器件结构及其制造方法

    公开(公告)号：US20070166887A1

    公开(公告)日：2007-07-19

    申请号：US11333618

    申请日：2006-01-17

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    IPC分类号： H01L21/82

    CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

    摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。