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    Semiconductor device structure and methods of manufacturing the same
    1.
    发明申请
    Semiconductor device structure and methods of manufacturing the same 有权
    半导体器件结构及其制造方法

    公开(公告)号：US20070166887A1

    公开(公告)日：2007-07-19

    申请号：US11333618

    申请日：2006-01-17

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    IPC分类号： H01L21/82

    CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

    摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

    Semiconductor device structure and methods of manufacturing the same
    2.
    发明授权
    Semiconductor device structure and methods of manufacturing the same 有权
    半导体器件结构及其制造方法

    公开(公告)号：US07512924B2

    公开(公告)日：2009-03-31

    申请号：US11333618

    申请日：2006-01-17

    申请人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    发明人： Hsien-Wei Chen ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Shin-Puu Jeng

    IPC分类号： G06F17/50

    CPC分类号： H01L27/0203 ,  G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

    摘要： A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.

    摘要翻译： 提供了一种生成半导体器件阵列布局的方法。 提供了第一布局，包括有源导电特征，围绕有源导电特征的边界区域以及除了有源导电特征和边界区域之外的开放区域。 提供了多个不同图案密度的虚拟模板，每个虚拟模板包括多个虚拟种子。 通过根据至少一个虚拟模板将假种子添加到开放区域来生成第二布局。

    System for heat dissipation in semiconductor devices
    3.
    发明授权
    System for heat dissipation in semiconductor devices 有权
    半导体器件散热系统

    公开(公告)号：US07420277B2

    公开(公告)日：2008-09-02

    申请号：US10801475

    申请日：2004-03-16

    申请人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

    发明人： Hsien-Wei Chen ,  Jiun-Lin Yeh ,  Shin-Puu Jeng ,  Yi-Lung Cheng

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/528 ,  H01L21/76834 ,  H01L21/76837 ,  H01L23/4334 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method and system for heat dissipation in semiconductor devices. In one example, an integrated circuit semiconductor device includes a semiconductor substrate; one or more metallurgy layers connected to the semiconductor substrate, and each of the one or more metallurgy layers includes: one or more conductive lines; and one or more dummy structures between the one or more conductive lines and at least two of the one or more dummy structures are connected; and one or more dielectric layers between the one or more metallurgy layers.

    摘要翻译： 本公开提供了一种用于半导体器件中散热的方法和系统。 在一个示例中，集成电路半导体器件包括半导体衬底; 连接到半导体衬底的一个或多个冶金层，并且所述一个或多个冶金层中的每一个包括：一个或多个导电线; 并且连接所述一个或多个导电线与所述一个或多个虚拟结构中的至少两个之间的一个或多个虚设结构; 以及一个或多个冶金层之间的一个或多个电介质层。

    Heat dissipation structure and method thereof
    4.
    发明申请
    Heat dissipation structure and method thereof 审中-公开
    散热结构及其方法

    公开(公告)号：US20050236716A1

    公开(公告)日：2005-10-27

    申请号：US10829583

    申请日：2004-04-22

    申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

    发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

    IPC分类号： H01L23/367 ,  H01L23/48 ,  H01L23/528

    CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

    摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

    Heat dissipation structure and method thereof
    6.
    发明申请
    Heat dissipation structure and method thereof 审中-公开
    散热结构及其方法

    公开(公告)号：US20060125090A1

    公开(公告)日：2006-06-15

    申请号：US11338551

    申请日：2006-01-24

    申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

    发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

    IPC分类号： H01L23/34

    CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

    摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

    Method for designing interconnect for a new processing technology
    9.
    发明申请
    Method for designing interconnect for a new processing technology 审中-公开
    用于设计新加工技术的互连的方法

    公开(公告)号：US20070158835A1

    公开(公告)日：2007-07-12

    申请号：US11332566

    申请日：2006-01-12

    申请人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

    发明人： Jian-Hong Lin ,  Hsueh-Chung Chen ,  Yi-Lung Cheng ,  Ta-Wei Lee ,  Chih-Tao Lin ,  Jyh-Kang Ting ,  Lee-Chung Lu

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.

    摘要翻译： 公开了一种用于在从参考处理技术缩放到预定处理技术的同时，分别在集成电路的两层中确定第一和第二导体之间的互连尺寸的方法。 该方法包括基于预定的处理技术来选择一组导体的设计规则，基于设计规则确定互连的矩形横截面积的第一侧的长度，以及用于缩放这种长度的缩放规则 将参考处理技术应用于预定处理技术，以及确定互连横截面积的第二侧的长度，以补偿由于从参考处理技术到预定处理技术的缩放而导致的互连电阻的增加 。

    Novel method to deposit carbon doped SiO2 films with improved film quality
    10.
    发明申请
    Novel method to deposit carbon doped SiO2 films with improved film quality 审中-公开
    用于提高膜质量的新型沉积碳掺杂SiO 2膜的方法

    公开(公告)号：US20050124151A1

    公开(公告)日：2005-06-09

    申请号：US10728215

    申请日：2003-12-04

    申请人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

    发明人： Yi-Lung Cheng ,  Ren-Haur Liu ,  Cheng-Hsiung Liu ,  Ying-Lang Wang ,  Hway-Chi Lin ,  Chien-Ming Chiu

    IPC分类号： C23C16/40 ,  H01L21/316 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76819

    摘要： A method is disclosed for depositing a Black Diamond layer in a CVD chamber. Trimethylsilane, O2, and Ar are flowed into the chamber at 300° C. to 400° C. with an O2:Ar:trimethylsilane flow rate ratio that is preferably 1:1.5:6. The resulting low k dielectric layer is formed with a higher deposition rate than when Ar is omitted and has a k value of about 3 that increases only slightly in O2 plasma. A higher density, hardness, and tensile strength are achieved in the Black Diamond layer when Ar is included in the deposition process. The addition of Ar in the deposition maintains film thickness uniformity below 2% for a longer period so that PM cleaning operations are less frequent and affords a lower fluorocarbon plasma etch rate to enable improved trench depth control in a damascene scheme. A lower leakage current and higher breakdown voltage in achieved in the resulting metal interconnect.

    摘要翻译： 公开了一种用于在CVD室中沉积黑金刚石层的方法。 三甲基硅烷O 2和Ar在300℃至400℃下以0:2:Ar:三甲基硅烷流速比流入室中，优选 1：1.5：6。 形成的低k电介质层的沉积速率高于省略Ar时的沉积速率，并且具有约3的K值仅在O 2等离子体中略微增加。 当在沉积过程中包含Ar时，在黑色金刚石层中获得较高的密度，硬度和拉伸强度。 沉积中Ar的添加将膜厚度均匀性维持在2％以下更长的时间，以便PM清洁操作较不频繁，并提供较低的氟碳等离子体蚀刻速率，从而能够改进镶嵌方案中的沟槽深度控制。 在所得到的金属互连中实现较低的漏电流和更高的击穿电压。