公开(公告)号：US10073715B2

公开(公告)日：2018-09-11

申请号：US15383738

申请日：2016-12-19

Applicant: Intel Corporation

Inventor： Chunling Hu ,  Tatiana Shpeisman ,  Rajkishore Barik ,  Justin E. Gottschlich

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4881 ,  G06F9/5027

Abstract: A dynamic runtime scheduling system includes task manager circuitry capable of detecting a correspondence in at least a portion of the output arguments from one or more first tasks with at least a portion of the input arguments to one or more second tasks. Upon detecting the output arguments from the first task represents a superset of the second task input arguments, the task manager circuitry apportions the first task into a plurality of new subtasks. At least one of the new subtasks includes output arguments having a 1:1 correspondence to the second task input arguments. Upon detecting the output arguments from an first task represents a subset of the second task input arguments, the task manager circuitry may autonomously apportion the second task into a plurality of new subtasks. At least one of the new subtasks may include input arguments having a 1:1 correspondence to first task output arguments.

公开(公告)号：US10001949B2

公开(公告)日：2018-06-19

申请号：US15160786

申请日：2016-05-20

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/44 ,  G06F12/0813 ,  G06F9/46

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/067 ,  G06F3/0673 ,  G06F9/44 ,  G06F9/466 ,  G06F9/467 ,  G06F12/0813

Abstract: Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an execution component for execution by the processor element to concurrently execute a software transaction and a hardware transaction according to a transactional memory process, a tracking component for execution by the processor element to activate a global lock to indicate that the software transaction is undergoing execution, and a finalization component for execution by the processor element to commit the software transaction and deactivate the global lock when execution of the software transaction completes, the finalization component to abort the hardware transaction when the global lock is active when execution of the hardware transaction completes. Other embodiments are described and claimed.

公开(公告)号：US09971627B2

公开(公告)日：2018-05-15

申请号：US14225804

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Irina Calciu ,  Justin E. Gottschlich ,  Tatiana Shpeisman ,  Gilles A. Pokam

IPC: G06F9/52 ,  G06F9/46

CPC classification number: G06F9/467 ,  G06F9/528

Abstract: In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first software transaction of a first software transaction mode and a second software transaction of a second software transaction mode and at least one hardware transaction of a first hardware transaction mode and at least one second hardware transaction of a second hardware transaction mode. In one example, the execution logic may be implemented within the processor. Other embodiments are described and claimed.

公开(公告)号：US09965320B2

公开(公告)日：2018-05-08

申请号：US14142475

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： Rolf Kassa ,  Justin E. Gottschlich ,  Shiliang Hu ,  Gilles A. Pokam ,  Robert C. Knauerhase

IPC: G06F9/46 ,  G06F15/00 ,  G06F9/52 ,  G06F11/07

CPC classification number: G06F9/467 ,  G06F9/528 ,  G06F11/0724 ,  G06F11/0772

Abstract: A processor is described comprising memory access conflict detection circuitry to identify a conflict pertaining to a transaction being executed by a thread that believes it has locked information within a memory. The processor also includes logging circuitry to construct and report out a packet if the memory access conflict detection circuitry identifies a conflict that causes the transaction to be aborted.

公开(公告)号：US09875108B2

公开(公告)日：2018-01-23

申请号：US13844817

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Gilles A. Pokam ,  Rolf Kassa ,  Klaus Danne ,  Tim Kranich ,  Cristiano L. Pereira ,  Justin E. Gottschlich ,  Shiliang Hu

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/32 ,  G06F12/0811 ,  G06F12/0842

CPC classification number: G06F9/3834 ,  G06F9/321 ,  G06F12/0811 ,  G06F12/0842 ,  Y02B70/12 ,  Y02D10/13

Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

公开(公告)号：US09697040B2

公开(公告)日：2017-07-04

申请号：US14226312

申请日：2014-03-26

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Gilles A. Pokam ,  Shiliang Hu ,  Rolf Kassa ,  Youfeng Wu ,  Irina Calciu

IPC: G06F9/44 ,  G06F9/45 ,  G06F9/46 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F9/467 ,  G06F11/34 ,  G06F11/362 ,  G06F11/3648

Abstract: A system is disclosed that includes a processor and a dynamic random access memory (DRAM). The processor includes a hybrid transactional memory (HyTM) that includes hardware transactional memory (HTM), and a program debugger to replay a program that includes an HTM instruction and that has been executed has been executed using the HyTM. The program debugger includes a software emulator that is to replay the HTM instruction by emulation of the HTM. Other embodiments are disclosed and claimed.

公开(公告)号：US20150363242A1

公开(公告)日：2015-12-17

申请号：US14833315

申请日：2015-08-24

Applicant: Intel Corporation

Inventor： Justin E. Gottschlich ,  Cristiano Ligieri Pereira ,  Gilles Pokam ,  Youfeng Wu

IPC: G06F9/52

CPC classification number: G06F9/52 ,  G06F11/3632

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage concurrent predicate expressions. An example method discloses inserting a first condition hook into a first thread, the first condition hook associated with a first condition, inserting a second condition hook into a second thread, the second condition hook associated with a second condition, preventing the second thread from executing until the first condition is satisfied, and identifying a concurrency violation when the second condition is satisfied.

Abstract translation: 公开了方法，装置，系统和制品以管理并发谓词表达。 一种示例性方法公开了将第一条件钩插入到第一线程中，与第一条件相关联的第一条件钩，将第二条件钩插入到第二线程中，与第二条件相关联的第二条件钩，防止第二线程执行 直到满足第一条件，并且当满足第二条件时识别并发冲突。

公开(公告)号：US20140281274A1

公开(公告)日：2014-09-18

申请号：US13844817

申请日：2013-03-16

Applicant: Intel Corporation

Inventor： Gilles A. Pokam ,  Rolf Kassa ,  Klaus Danne ,  Tim Kranich ,  Cristiano L. Pereira ,  Justin E. Gottschlich ,  Shiliang Hu

IPC: G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/321 ,  G06F12/0811 ,  G06F12/0842 ,  Y02B70/12 ,  Y02D10/13

Abstract: A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.

Abstract translation: 一种用于在存在复杂多操作指令的情况下记录共享存储器访问的交错的系统，处理器和方法。 公开了对指令原子性（IA）的扩展，使得如果硬件已经记录了由于指令原子性违规（IAV）引起的依赖关系，则软件可以推断关于多操作执行的部分信息。 通过监视多操作指令的进度，不需要复杂的多操作仿真。

公开(公告)号：US20240257294A1

公开(公告)日：2024-08-01

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

CPC classification number: G06T1/20 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41 ,  G06F2009/45583

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US11922535B2

公开(公告)日：2024-03-05

申请号：US18168207

申请日：2023-02-13

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41

CPC classification number: G06T1/20 ,  G06F9/45533 ,  G06F9/5061 ,  G06F9/5094 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F8/41 ,  G06F2009/45583

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.