公开(公告)号：US09484888B2

公开(公告)日：2016-11-01

申请号：US13719527

申请日：2012-12-19

Applicant: Intel Corporation

Inventor： Yong Yang ,  Zuoguo Wu

IPC: H03K3/00 ,  H03H11/24 ,  H03F3/45

CPC classification number: H03H11/245 ,  H03F3/45197

Abstract: Described is an apparatus which comprises: a first voltage follower; a second voltage follower; and a pass-gate including a p-type transistor in parallel to an n-type transistor, wherein gate terminal of the p-type transistor is controlled by an output of the first voltage follower, and wherein gate terminal of the n-type transistor is controlled by an output of the second voltage follower.

Abstract translation: 描述了一种装置，包括：第一电压跟随器; 第二电压跟随器; 以及包括与n型晶体管并联的p型晶体管的通过栅极，其中p型晶体管的栅极端子由第一电压跟随器的输出控制，并且其中n型晶体管的栅极端子 由第二电压跟随器的输出控制。

公开(公告)号：US20160283429A1

公开(公告)日：2016-09-29

申请号：US14669975

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Mark S. Birrittella ,  Ishwar Agarwal ,  Lip Khoon Teh ,  Su Wei Lim ,  Anoop Kumar Upadhyay

IPC: G06F13/40 ,  G06F13/36 ,  G01R31/317

CPC classification number: G06F13/4022 ,  G06F13/36 ,  G06F13/4068

Abstract: A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that [k/n] hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.

Abstract translation: 诸如逻辑PHY的片上系统可以被划分为具有固定路由的硬IP块和具有灵活路由的软IP块。 每个硬IP块可以提供固定数量的车道。 使用p硬IP块，其中每个块提供n个数据通道，h = n * p提供总硬IP数据通道。 在系统设计要求k个总数据通道的情况下，k≠h可以使得[k / n]硬IP块提供h = n * p可用的硬IP数据通道。 在这种情况下，h-k通道可能被禁用。 在发生通道反转的情况下，例如在硬IP和软IP之间，可以通过使用软IP内的多路复用器可编程开关来避免路由路由。

公开(公告)号：US20160191034A1

公开(公告)日：2016-06-30

申请号：US14583139

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer ,  Gerald S. Pasdast ,  Todd A. Hinck ,  David M. Lee ,  Narasimha R. Lanka

IPC: H03K5/26 ,  G01R31/04 ,  H03L9/00

CPC classification number: H03K5/26 ,  G01R31/041 ,  G06F1/3296 ,  G06F13/4291 ,  H03K5/131 ,  H03L9/00

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract translation: 在一个示例中，公开了一种用于以高性能互连（HPI）为中心的系统和方法。 当互连从休眠状态上电时，可能需要“中心”时钟信号，以确保在正确的时间读取数据。 可以使用多相方法，其中第一相包括参考电压扫描以识别最佳参考电压。 第二阶段包括相位扫描以识别最佳相位。 第三扫描包括二维“眼”阶段，其中测试从前两次扫描得到的二维眼睛内的多个值。 在每种情况下，最佳值是导致多个通道中最小位错误的值。 在一个示例中，第二和第三阶段以软件执行，并且可以包括测试“受害者”通道，具有具有互补位模式的相邻“侵略者”通道。

公开(公告)号：US20160188519A1

公开(公告)日：2016-06-30

申请号：US14583607

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Mahesh Wagh ,  Zuoguo Wu ,  Venkatraman Iyer

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4265

Abstract: In an example, a high-performance interconnect (HPI) is provisioned without a separate stream lane. To provide equivalent functionality, stream lane data are provided within data lines during idle periods. Because one stream lane may be provided per 20 data lanes, elimination of the stream lane saves approximately 5% of area. In a pre-data time, the 20 data lanes may be brought high from midrail to represent one species of data (for example, Intel® in-die interconnect (IDI)), and brought low to represent a second species of data (for example, Intel® on-chip system fabric (IOSF)). To represent additional species of data, such as link control packets (LCPs) for example, lanes can be divided into two or more groups, and a single bit can be encoded into each group. LCP can also be encoded into a post-data time, for example by ceasing flit traffic and manipulating a “VALID” lane from midrail to 0 or 1.

Abstract translation: 在一个示例中，高性能互连（HPI）被提供而没有单独的流线。 为了提供等效的功能，在空闲周期内在数据线内提供流道数据。 因为每20条数据通道可以提供一条流道，所以流线路的消除节省了大约5％的面积。 在预数据时间内，20个数据通道可能会从中段带来很高的，以表示一种数据（例如，英特尔®芯片间互连（IDI）），并带来了低的代表第二种数据（对于 例如英特尔®片上系统架构（IOSF））。 为了表示例如链路控制分组（LCP）的附加数据种类，可以将通道划分为两个或更多个组，并且可以将单个比特编码到每个组中。 LCP也可以被编码成后数据时间，例如通过停止飞行交通并且操纵从中途到0或1的“有效”通道。

公开(公告)号：US20160182257A1

公开(公告)日：2016-06-23

申请号：US14582105

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Daniel Froelich ,  Zuoguo Wu ,  Anupriya Sriramulu

IPC: H04L25/02 ,  H04L25/03

CPC classification number: H04L25/0262 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: An apparatus is described herein. The apparatus comprises a physical layer (PHY), wherein analog circuitry of the physical layer is to determine a data rate. The apparatus also comprises a media access layer (MAC), wherein the media access layer is to receive the data rate from the physical layer.

Abstract translation: 这里描述了一种装置。 该装置包括物理层（PHY），其中物理层的模拟电路用于确定数据速率。 该装置还包括媒体接入层（MAC），其中媒体接入层将从物理层接收数据速率。