公开(公告)号：US11599497B2

公开(公告)日：2023-03-07

申请号：US17008363

申请日：2020-08-31

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Mohiuddin M. Mazumder ,  Jong-Ru Guo ,  Anupriya Sriramulu ,  Narasimha Lanka ,  Timothy Wig ,  Jeff Morriss

IPC: G06F15/173 ,  H01L23/522 ,  H03K19/17736 ,  G06F15/16 ,  H01L21/768 ,  G06F9/28

Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

公开(公告)号：US20180253398A1

公开(公告)日：2018-09-06

申请号：US15636738

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Mohiuddin M. Mazumder ,  Jong-Ru Guo ,  Anupriya Sriramulu ,  Narasimha Lanka ,  Timothy Wig ,  Jeff Morriss

IPC: G06F15/173 ,  H01L23/522 ,  H03K19/177 ,  G06F15/16 ,  H01L21/768 ,  G06F9/28

Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

公开(公告)号：US10789201B2

公开(公告)日：2020-09-29

申请号：US15636738

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Zuoguo Wu ,  Debendra Das Sharma ,  Mohiuddin M. Mazumder ,  Jong-Ru Guo ,  Anupriya Sriramulu ,  Narasimha Lanka ,  Timothy Wig ,  Jeff Morriss

IPC: G06F15/173 ,  H01L23/522 ,  H03K19/17736 ,  G06F15/16 ,  H01L21/768 ,  G06F9/28

Abstract: A device includes a receiver to receive one or more training sequences during a training of a link, where the link connects two devices. The device may include agent logic to determine, from the one or more training sequences, a number of extension devices on the link between the two devices, and determine that the number of extension devices exceeds a threshold number. The device may include a transmitter to send a plurality of clock compensation ordered sets on the link based on determining that the number of extension devices exceeds a threshold number.

公开(公告)号：US09935063B2

公开(公告)日：2018-04-03

申请号：US15201375

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Yu Amos Zhang ,  Jihwan Kim ,  Ajay Balankutty ,  Anupriya Sriramulu ,  MD. Mohiuddin Mazumder ,  Frank O'Mahony ,  Zuoguo Wu ,  Kemal Aygun

IPC: H01L23/00 ,  H01L23/64 ,  H02H9/04 ,  H01L27/02 ,  H01L23/66

CPC classification number: H01L23/645 ,  H01L23/66 ,  H01L27/0248 ,  H01L27/0288 ,  H02H9/046

Abstract: Integrated circuit (IC) chip “on-die” inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a surface contact of the chip. Such inductor structures may include a first data signal inductor having (1) a second end electrically coupled to an electrostatic discharge (ESD) circuit and a capacitance value of that circuit, and (2) a first end electrically coupled to a the data signal surface contact and to a capacitance value at that contact; and a second data signal inductor having (1) a second end electrically coupled to the data signal circuit and a capacitance value of that circuit, (2) a first end electrically coupled to the second end of the first data signal inductor, and to the capacitance value of the ESD circuit. Inductor values of the first and second inductors may be selected to cancel out the capacitance values to improve signaling.

公开(公告)号：US20160182257A1

公开(公告)日：2016-06-23

申请号：US14582105

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Daniel Froelich ,  Zuoguo Wu ,  Anupriya Sriramulu

IPC: H04L25/02 ,  H04L25/03

CPC classification number: H04L25/0262 ,  H04L25/03057 ,  H04L25/03343 ,  H04L25/03885

Abstract: An apparatus is described herein. The apparatus comprises a physical layer (PHY), wherein analog circuitry of the physical layer is to determine a data rate. The apparatus also comprises a media access layer (MAC), wherein the media access layer is to receive the data rate from the physical layer.

Abstract translation: 这里描述了一种装置。 该装置包括物理层（PHY），其中物理层的模拟电路用于确定数据速率。 该装置还包括媒体接入层（MAC），其中媒体接入层将从物理层接收数据速率。