公开(公告)号：US11527481B2

公开(公告)日：2022-12-13

申请号：US17090933

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Choong Kooi Chee ,  Bok Eng Cheah ,  Teong Guan Yew ,  Jackson Chung Peng Kong ,  Loke Yip Foo

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

公开(公告)号：US11521932B2

公开(公告)日：2022-12-06

申请号：US17025990

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Jenny Shio Yin Ong ,  Ping Ping Ooi ,  Seok Ling Lim

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: Disclosed embodiments include composite-bridge die-to-die interconnects that are on a die side of an integrated-circuit package substrate and that contacts two IC dice and a passive device that is in a molding material, where the molding material also contacts the two IC dice.

公开(公告)号：US11508660B2

公开(公告)日：2022-11-22

申请号：US17089745

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Seok Ling Lim ,  Bok Eng Cheah ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/56 ,  H01L25/065 ,  H01L23/31 ,  H01L23/538 ,  H01L23/50

Abstract: A semiconductor package including a molded power delivery module arranged between a package substrate and a semiconductor chip and including a plurality of input conductive structures and a plurality of reference conductive structures, wherein the input conductive structures alternate between the plurality of reference conductive structures, wherein the input conductive structure is electrically coupled with a chip input voltage terminal and a package input voltage terminal, wherein each of the plurality of reference conductive structures are electrically coupled with a semiconductor chip reference terminal and a package reference terminal.

公开(公告)号：US11482481B2

公开(公告)日：2022-10-25

申请号：US16888155

申请日：2020-05-29

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi ,  Lee Fueng Yap ,  Chan Kim Lee

IPC: H05K1/18 ,  H01L23/498 ,  H01L25/16 ,  H01L25/18

Abstract: An electronic device is disclosed. In one example, the electronic device includes a circuit board comprising a recess a package in the recess, a semiconductor die coupled to the first side of the package, and a bridge extending from the first side of the package to the circuit board wherein the bridge electrically couples the package to the circuit board.

公开(公告)号：US11456516B2

公开(公告)日：2022-09-27

申请号：US17030634

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Ling Li Ong ,  Kin Wai Lee ,  Bok Eng Cheah ,  Yang Liang Poh ,  Yean Ling Soon

IPC: H01P3/08 ,  H01L23/552 ,  H01L23/528 ,  H01L23/66

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.

公开(公告)号：US11411290B2

公开(公告)日：2022-08-09

申请号：US16305355

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Hungying L. Lo ,  Bok Eng Cheah

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01L23/498

Abstract: One embodiment provides an apparatus. The apparatus includes a first signal trace and a current return path. The current return path includes a plurality of portions. The plurality of portions includes a first portion, a second portion and a third portion. The first portion is included in a first power plane. The second portion is included in a second power plane coplanar with the first power plane and separated from the first power plane by a split. The third portion spans the split and is included in a reference voltage plane. The reference voltage plane is coplanar with the first signal trace. The reference voltage plane is separated from the first power plane and the second power plane by a dielectric material.

公开(公告)号：US11363717B2

公开(公告)日：2022-06-14

申请号：US17090949

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ranjul Balakrishnan

IPC: H05K1/18 ,  H05K1/16

Abstract: For circuit boards that may be used in computing devices, a horizontal inductor, or an array of such inductors, may be coupled to a circuit board having a plurality of signal routing lines in a second layer from a surface of the circuit board and the horizontal inductor is positioned over these signal routing lines and may generate magnetic field lines that directionally follow the signal routing lines. The horizontal inductor may have a coiled wire with a central axis that is oriented horizontally with the surface of the circuit board. The horizontal inductor, or an array of such inductors, may be coupled to a support board attached to the circuit board.

公开(公告)号：US11355458B2

公开(公告)日：2022-06-07

申请号：US16469073

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Jackson Chung Peng Kong ,  Bok Eng Cheah ,  Ping Ping Ooi ,  Kooi Chi Ooi

IPC: H01L23/64 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00

Abstract: A device and method of utilizing conductive thread interconnect cores. Substrates using conductive thread interconnect cores are shown. Methods of creating a conductive thread interconnect core are shown.

公开(公告)号：US20220068836A1

公开(公告)日：2022-03-03

申请号：US17522603

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.

公开(公告)号：US11195801B2

公开(公告)日：2021-12-07

申请号：US16663853

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Seok Ling Lim ,  Jenny Shio Yin Ong ,  Jackson Chung Peng Kong ,  Kooi Chi Ooi

IPC: H01L23/552 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528

Abstract: Two conductive reference layers are embedded in a semiconductor package substrate. The embedded reference layers facilitate low electromagnetic noise coupling between adjacent signals for semiconductor device package.