公开(公告)号：US20210184326A1

公开(公告)日：2021-06-17

申请号：US17030634

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Ling Li Ong ,  Kin Wai Lee ,  Bok Eng Cheah ,  Yang Liang Poh ,  Yean Ling Soon

IPC: H01P3/08 ,  H01L23/66 ,  H01L23/528 ,  H01L23/552

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a. first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.

公开(公告)号：US11456516B2

公开(公告)日：2022-09-27

申请号：US17030634

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Ling Li Ong ,  Kin Wai Lee ,  Bok Eng Cheah ,  Yang Liang Poh ,  Yean Ling Soon

IPC: H01P3/08 ,  H01L23/552 ,  H01L23/528 ,  H01L23/66

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include an assembly having asymmetrically situated conductors. In selected examples, the assembly includes a ground plane, a central shield portion, a first side shield portion on a first side, a second side shield portion on a second side, a first conductor asymmetrically situated between the central shield portion and the first side shield portion, a second conductor asymmetrically situated between the central shield portion and the second side shield portion, and dielectric within the assembly.

公开(公告)号：US20230420379A1

公开(公告)日：2023-12-28

申请号：US17848059

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Eng Huat Goh ,  Seok Ling Lim ,  Hazwani Jaffar ,  Yean Ling Soon

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/552 ,  H01L23/66

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5381 ,  H01L23/5385 ,  H01L23/552 ,  H01L23/66 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L24/08

Abstract: IC device package routing with metallization features comprising a pseudo-stripline architecture in which the stripline structure is provisioned, in part, by a routing structure separate from routing within the package substrate. A signal route within top metallization level of a package substrate may be electrically shielded, in part, with a metallization feature within a redistribution layer (RDL) of a routing structure that couples one or more IC chips to the package substrate. Accordingly, a package substrate may have fewer levels of metallization, reduced thickness, and/or lower cost while the IC device package still offers excellent EMI performance.