公开(公告)号：US11917053B2

公开(公告)日：2024-02-27

申请号：US17707629

申请日：2022-03-29

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

CPC classification number: H04L9/0643 ,  G06F7/503 ,  G06F9/3012 ,  H04L9/3247

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US11750402B2

公开(公告)日：2023-09-05

申请号：US17534158

申请日：2021-11-23

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3247 ,  G06F9/3877 ,  H04L9/0643 ,  H04L9/0861 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US11727260B2

公开(公告)日：2023-08-15

申请号：US17484828

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Jack T. Kavalieros ,  Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Uygar Avci ,  Gregory K. Chen ,  Amrita Mathuriya ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul ,  Nazila Haratipour ,  Van H. Le

IPC: G06N3/063 ,  H01L27/108 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11 ,  G11C11/54 ,  G11C7/10 ,  G11C11/419 ,  G11C11/409 ,  G11C11/22 ,  G06N3/065 ,  H10B10/00 ,  H10B12/00 ,  H10B53/00

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04 ,  G11C7/1006 ,  G11C7/1039 ,  G11C11/54 ,  H10B10/18 ,  H10B12/01 ,  H10B12/033 ,  H10B12/20 ,  H10B12/50 ,  H10B53/00 ,  G11C11/221 ,  G11C11/409 ,  G11C11/419

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit for implementing a neural network disposed on a semiconductor chip. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The mathematical computation circuit includes an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：US20230004681A1

公开(公告)日：2023-01-05

申请号：US17930326

申请日：2022-09-07

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Raghavan Kumar ,  Sanu Mathew

IPC: G06F21/75 ,  G06F21/31 ,  G06F21/79

Abstract: A method comprises generating, during an enrollment process conducted in a controlled environment, a dark bit mask comprising a plurality of state information values derived from a plurality of entropy sources at a plurality of operating conditions for an electronic device, and using at least a portion of the plurality of state information values to generate a set of challenge-response pairs for use in an authentication process for the electronic device.

公开(公告)号：US11416165B2

公开(公告)日：2022-08-16

申请号：US16160482

申请日：2018-10-15

Applicant: INTEL CORPORATION

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young ,  Abhishek Sharma

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/1081 ,  G06N3/04 ,  G06F12/0802 ,  G06N3/063 ,  G06F12/0875 ,  G06F12/0897

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.

公开(公告)号：US20220058167A1

公开(公告)日：2022-02-24

申请号：US17128836

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Raghavan Kumar

IPC: G06F16/21 ,  G06F16/22 ,  H04L9/32

Abstract: Techniques and mechanisms to facilitate Bitcoin mining operations which support version rolling. In an embodiment, Bitcoin mining circuitry comprises a first scheduler, a first digest, a second scheduler and a second digest arranged in a pipeline configuration. Hash circuitry calculates a first plurality of hashes each based on first bits of a Merkle root, and on a different respective identifier of a Bitcoin protocol version. The first scheduler generates first message schedules each based on second bits of the Merkle root, and on a different respective nonce value. In another embodiment, the first scheduler successively provides the first message schedules to the first digest, wherein, for each such providing of one of the first message schedules, the first digest, second scheduler and second digest successively generate second hashes each based on the provided one of the first message schedules, and on a different respective one of the first hashes.

公开(公告)号：US11240039B2

公开(公告)日：2022-02-01

申请号：US16455921

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  H04L9/06 ,  G06F9/38 ,  H04L9/08

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US11195079B2

公开(公告)日：2021-12-07

申请号：US15821123

申请日：2017-11-22

Applicant: INTEL CORPORATION

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Phil Knag ,  Raghavan Kumar ,  Ram K. Krishnamurthy

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N3/06

Abstract: In one embodiment, a processor comprises a first neuro-synaptic core comprising first circuitry to configure the first neuro-synaptic core as a neuron core responsive to a first value specified by a configuration parameter; and configure the first neuro-synaptic core as a synapse core responsive to a second value specified by the configuration parameter.

公开(公告)号：US11157799B2

公开(公告)日：2021-10-26

申请号：US16299014

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Huseyin E. Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06E1/00 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.

公开(公告)号：US10922607B2

公开(公告)日：2021-02-16

申请号：US15394976

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Abhronil Sengupta ,  Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag

IPC: G06N3/08 ,  G06N3/04

Abstract: In one embodiment, a processor is to store a membrane potential of a neural unit of a neural network; and calculate, at a particular time-step of the neural network, a change to the membrane potential of the neural unit occurring over multiple time-steps that have elapsed since the last time-step at which the membrane potential was updated, wherein each of the multiple time-steps that have elapsed since the last time-step is associated with at least one input to the neural unit that affects the membrane potential of the neural unit.