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    IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRATE BASED ON CRITERIA RELATED TO THE NEUROSYNAPTIC SUBSTRATE
    72.
    发明申请
    IMPLEMENTING A NEURAL NETWORK ALGORITHM ON A NEUROSYNAPTIC SUBSTRATE BASED ON CRITERIA RELATED TO THE NEUROSYNAPTIC SUBSTRATE 审中-公开
    基于与神经生物基质相关的标准，在神经生物学基底上实施神经网络算法

    公开(公告)号：US20160335535A1

    公开(公告)日：2016-11-17

    申请号：US14662096

    申请日：2015-03-18

    申请人： International Business Machines Corporation

    发明人： Arnon Amir ,  Rathinakumar Appuswamy ,  Pallab Datta ,  Myron D. Flickner ,  Paul A. Merolla ,  Dharmendra S. Modha ,  Benjamin G. Shaw

    IPC分类号： G06N3/063 ,  G06N3/04

    CPC分类号： G06N3/063 ,  G06N3/04

    摘要： One embodiment of the invention provides a system for mapping a neural network onto a neurosynaptic substrate. The system comprises a reordering unit for reordering at least one dimension of an adjacency matrix representation of the neural network. The system further comprises a mapping unit for selecting a mapping method suitable for mapping at least one portion of the matrix representation onto the substrate, and mapping the at least one portion of the matrix representation onto the substrate utilizing the mapping method selected. The system further comprises a refinement unit for receiving user input regarding at least one criterion relating to accuracy or resource utilization of the substrate. The system further comprises an evaluating unit for evaluating each mapped portion against each criterion. Each mapped portion that fails to satisfy a criterion may be remapped to allow trades offs between accuracy and resource utilization of the substrate.

    摘要翻译： 本发明的一个实施例提供了一种用于将神经网络映射到神经突触基底上的系统。 该系统包括重排序单元，用于对神经网络的邻接矩阵表示的至少一个维度重新排序。 该系统还包括映射单元，用于选择适于将矩阵表示的至少一部分映射到衬底上的映射方法，以及使用所选择的映射方法将矩阵表示的至少一部分映射到衬底上。 该系统还包括用于接收关于与衬底的精度或资源利用有关的至少一个准则的用户输入的细化单元。 该系统还包括评估单元，用于针对每个标准评估每个映射部分。 不能满足标准的每个映射部分可以被重新映射以允许在衬底的精度和资源利用之间进行交易。

    POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS
    74.
    发明申请
    POWER DRIVEN SYNAPTIC NETWORK SYNTHESIS 审中-公开
    POWER DRIVEN SYNAPTIC网络合成

    公开(公告)号：US20160132767A1

    公开(公告)日：2016-05-12

    申请号：US14537826

    申请日：2014-11-10

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhuo Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC分类号： G06N3/063 ,  G06N3/04 ,  G06F17/30

    摘要： Embodiments of the present invention relate to providing power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for power-driven synaptic network synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores. An arrangement of the synaptic cores is determined by minimizing the wire length.

    摘要翻译： 本发明的实施例涉及在多核神经突触网络中提供功率最小化。 在本发明的一个实施例中，提供了一种用于电源突触网络合成的方法和计算机程序产品。 神经突触网络的功耗被建模为线长度。 神经突触网络包括多个神经突触核。 通过最小化导线长度来确定突触核心的布置。

    Neural network weight distribution from a grid of memory elements
    76.
    发明授权
    Neural network weight distribution from a grid of memory elements 有权

    公开(公告)号：US11521085B2

    公开(公告)日：2022-12-06

    申请号：US16842035

    申请日：2020-04-07

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Jun Sawada ,  Dharmendra S. Modha ,  Andrew S. Cassidy ,  John V. Arthur ,  Tapan K. Nayak ,  Carlos O. Otero ,  Brian Taba ,  Filipp A. Akopyan ,  Pallab Datta

    IPC分类号： G06N5/04 ,  G06N3/063 ,  G06F17/15 ,  G06F17/16

    摘要： Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

    Fault-tolerant power-driven synthesis
    78.
    发明授权
    Fault-tolerant power-driven synthesis 有权

    公开(公告)号：US11301757B2

    公开(公告)日：2022-04-12

    申请号：US16696968

    申请日：2019-11-26

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： Charles J. Alpert ,  Pallab Datta ,  Myron D. Flickner ,  Zhou Li ,  Dharmendra S. Modha ,  Gi-Joon Nam

    IPC分类号： G06N3/10

    摘要： Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.