Cache coherency protocol permitting sharing of a locked data granule
    71.
    发明授权
    Cache coherency protocol permitting sharing of a locked data granule 失效
    缓存一致性协议允许共享锁定的数据粒子

    公开(公告)号:US06629209B1

    公开(公告)日:2003-09-30

    申请号:US09437185

    申请日:1999-11-09

    IPC分类号: G06F1200

    CPC分类号: G06F12/0831

    摘要: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.

    摘要翻译: 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态,指示符位和锁定采集例程以提高高速缓存性能。 额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

    Extended cache coherency protocol with a modified store instruction lock release indicator
    72.
    发明授权
    Extended cache coherency protocol with a modified store instruction lock release indicator 失效
    扩展缓存一致性协议,具有修改后的存储指令锁定释放指示器

    公开(公告)号:US06625701B1

    公开(公告)日:2003-09-23

    申请号:US09437183

    申请日:1999-11-09

    IPC分类号: G06F1214

    CPC分类号: G06F12/0811 G06F12/0815

    摘要: A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.

    摘要翻译: 多处理器数据处理系统需要仔细管理以保持高速缓存一致性。 使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。 所公开的系统提供附加的高速缓存状态,指示符位和锁定采集例程以提高高速缓存性能。 特别地,由于多个处理器竞争相同的高速缓存行,所以丢失了大量的处理器时间,这确定了另一个处理器的高速缓存行锁定是否已被释放,并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。 优选实施例提供具有高速缓存存储命令的指示符位,其特别地指示存储还是否用作锁定释放。

    Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer
    73.
    发明授权
    Method and system for controlling information flow in a high frequency digital system from a producer to a buffering consumer via an intermediate buffer 失效
    用于通过中间缓冲器控制从生产者到缓冲消费者的高频数字系统中的信息流的方法和系统

    公开(公告)号:US06598086B1

    公开(公告)日:2003-07-22

    申请号:US09436961

    申请日:1999-11-09

    IPC分类号: G06F1516

    摘要: An information handling system includes a plurality of sequentially connected units including a first unit, a second unit and a third unit. Packets of information flow from the first unit directly to the second unit and then to the third unit, and each of the plurality of units provides a respective dynamic output indication indicating if that unit output a packet. The information handling system further includes a control unit that determines, utilizing all of the plurality of dynamic output indications, packet buffering capacities of the plurality of units, and guaranteed packet flows between adjacent ones of the plurality of units, if the first unit can output a packet directly to the second unit without packet loss. In response to this determination, the control unit outputs a control signal to the first unit.

    摘要翻译: 信息处理系统包括多个依次连接的单元,包括第一单元,第二单元和第三单元。 信息包从第一单元直接传输到第二单元,然后流向第三单元,并且多个单元中的每个单元提供指示该单元是否输出分组的相应的动态输出指示。 所述信息处理系统还包括:控制单元,其确定利用所述多个动态输出指示中的所有多个单元的分组缓冲能力以及所述多个单元中的相邻单元之间的保证的分组流,如果所述第一单元可以输出 一个数据包直接连到第二个单元没有丢包。 响应于该确定,控制单元向第一单元输出控制信号。

    Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line
    74.
    发明授权
    Cache coherency protocol employing a read operation including a programmable flag to indicate deallocation of an intervened cache line 有权
    缓存一致性协议采用包括可编程标志的读取操作来指示干预的高速缓存行的解除分配

    公开(公告)号:US06345342B1

    公开(公告)日:2002-02-05

    申请号:US09437177

    申请日:1999-11-09

    IPC分类号: G06F1200

    CPC分类号: G06F12/0831

    摘要: A novel cache coherency protocol provides a modified-unsolicited (Mu) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the Mu state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The Mu state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the Mu state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

    摘要翻译: 一种新颖的高速缓存一致性协议提供修改的非请求(Mu)高速缓存状态,以指示保持在高速缓存行中的值已经被修改(即,当前不符合系统存储器),但是被另一个处理单元修改,而不是由 与当前包含Mu状态的值的高速缓存相关联的处理单元,并且该值被保持为排除任何其他水平相邻的高速缓存。 因为该值是唯一保留的,所以可以在该高速缓存中修改该值,而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果,可以应用Mu状态。 读取请求可以包括用于指示请求的高速缓存能够利用Mu状态的标志。 或者,可以向标记提供干预数据,以指示请求的高速缓存应该利用修改的未经请求的状态。

    High performance multiprocessor system with modified-unsolicited cache state
    75.
    发明授权
    High performance multiprocessor system with modified-unsolicited cache state 失效
    具有修改的主动缓存状态的高性能多处理器系统

    公开(公告)号:US06321306B1

    公开(公告)日:2001-11-20

    申请号:US09437179

    申请日:1999-11-09

    IPC分类号: G06F1212

    CPC分类号: G06F12/0831

    摘要: A novel cache coherency protocol provides a modified-unsolicited (MU) cache state to indicate that a value held in a cache line has been modified (i.e., is not currently consistent with system memory), but was modified by another processing unit, not by the processing unit associated with the cache that currently contains the value in the MU state, and that the value is held exclusive of any other horizontally adjacent caches. Because the value is exclusively held, it may be modified in that cache without the necessity of issuing a bus transaction to other horizontal caches in the memory hierarchy. The MU state may be applied as a result of a snoop response to a read request. The read request can include a flag to indicate that the requesting cache is capable of utilizing the MU state. Alternatively, a flag may be provided with intervention data to indicate that the requesting cache should utilize the modified-unsolicited state.

    摘要翻译: 一种新颖的高速缓存一致性协议提供修改的非请求(MU)高速缓存状态,以指示保持在高速缓存行中的值已被修改(即,当前不符合系统存储器),但是被另一个处理单元修改,而不是由 与当前包含MU状态的值的高速缓存相关联的处理单元,并且该值被保持为任何其他水平相邻的高速缓存。 因为该值是唯一保留的,所以可以在该高速缓存中修改该值,而不需要向存储器层级中的其他水平高速缓存发出总线事务。 作为对读取请求的窥探响应的结果,可以应用MU状态。 读取请求可以包括用于指示请求的高速缓存能够利用MU状态的标志。 或者,可以向标记提供干预数据,以指示请求的高速缓存应该利用修改的未经请求的状态。

    Automatic cache prefetch timing with dynamic trigger migration
    76.
    发明授权
    Automatic cache prefetch timing with dynamic trigger migration 失效
    自动缓存预取定时与动态触发迁移

    公开(公告)号:US5809566A

    公开(公告)日:1998-09-15

    申请号:US702407

    申请日:1996-08-14

    IPC分类号: G06F9/38 G06F12/08

    摘要: Dynamic migration of a cache prefetch request is performed. A prefetch candidate table maintains at least one prefetch candidate which may be executed as a prefetch request. The prefetch candidate includes one or more trigger addresses which correspond to locations in the instruction stream where the prefetch candidate is to be executed as a prefetch request. A jump history table maintains a record of target addresses of program branches which have been executed. The trigger addresses in the prefetch candidate are defined by the target addresses of recently executed program branches maintained in the jump history table. A pending prefetch table maintains a record of executed prefetch requests. When an operation such as a cache miss, cache hit, touch instruction or program branch is identified, the pending prefetch table is scanned to determine whether a prefetch request has been executed. If a prefetch request has been executed, the prefetch candidate which was used to execute that prefetch request is updated. That is, a new trigger address in the prefetch candidate is selected in order to reduce access latency.

    摘要翻译: 执行缓存预取请求的动态迁移。 预取候选表维持至少一个可以作为预取请求执行的预取候选。 预取候选包括一个或多个触发地址,其对应于将作为预取请求执行预取候选的指令流中的位置。 跳转历史记录表维护已执行的程序分支的目标地址记录。 预取候选中的触发地址由保持在跳转历史表中的最近执行的程序分支的目标地址定义。 待处理的预取表维护执行的预取请求的记录。 当识别诸如高速缓存未命中,缓存命中,触摸指令或程序分支的操作​​时,扫描挂起的预取表以确定是否已经执行了预取请求。 如果已经执行了预取请求,则更新用于执行该预取请求的预取候选。 也就是说,选择预取候选中的新的触发地址以便减少访问延迟。

    Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers
    78.
    发明授权
    Concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers 失效
    在跟踪过程和使用可编程可变数量的共享内存写入缓冲区的非跟踪过程之间同时共享内存控制器

    公开(公告)号:US07913123B2

    公开(公告)日:2011-03-22

    申请号:US12210005

    申请日:2008-09-12

    IPC分类号: G06F11/00

    CPC分类号: G06F11/2268 G06F11/348

    摘要: An apparatus and computer program product are disclosed for, in a processor, concurrently sharing a memory controller among a tracing process and non-tracing processes using a programmable variable number of shared memory write buffers. A hardware trace facility captures hardware trace data in a processor. The hardware trace facility is included within the processor. The hardware trace data is transmitted to a system memory utilizing a system bus. The system memory is included within the system. The system bus is capable of being utilized by processing units included in the processing node while the hardware trace data is being transmitted to the system bus. Part of system memory is utilized to store the trace data. The system memory is capable of being accessed by processing units in the processing node other than the hardware trace facility while part of the system memory is being utilized to store the trace data.

    摘要翻译: 公开了一种装置和计算机程序产品,用于在处理器中使用可编程可变数量的共享存储器写缓冲器在跟踪处理和非跟踪处理之间共享存储器控制器。 硬件跟踪设备捕获处理器中的硬件跟踪数据。 硬件跟踪工具包含在处理器内。 使用系统总线将硬件跟踪数据传输到系统存储器。 系统内存包含在系统中。 当将硬件跟踪数据发送到系统总线时,系统总线能够被包括在处理节点中的处理单元利用。 系统内存的一部分用于存储跟踪数据。 系统存储器能够被处理节点除硬件跟踪设备之外的处理单元访问,同时系统存储器的一部分用于存储跟踪数据。

    Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
    79.
    发明授权
    Enhanced processor virtualization mechanism via saving and restoring soft processor/system states 失效
    通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制

    公开(公告)号:US07849298B2

    公开(公告)日:2010-12-07

    申请号:US12352462

    申请日:2009-01-12

    摘要: A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

    摘要翻译: 公开了一种方法和系统,用于在接收到处理器的处理中断时,保存对于在处理器中执行处理不重要的软​​状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地,软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口,这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后,当再次执行处理时,可以从存储器恢复存储的软状态。

    INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW
    80.
    发明申请
    INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW 有权
    信息处理系统,具有立即调度在双存储单元缓存中的负载运算,具有单个分配到写/读数据流

    公开(公告)号:US20100268890A1

    公开(公告)日:2010-10-21

    申请号:US12424228

    申请日:2009-04-15

    IPC分类号: G06F12/08

    CPC分类号: G06F12/0846 G06F12/0897

    摘要: An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.

    摘要翻译: 信息处理系统(IHS)包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制,其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑,其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库,使得一个存储体可以执行加载操作,而另一个存储体执行存储操作。 缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。