公开(公告)号：US5629928A

公开(公告)日：1997-05-13

申请号：US570840

申请日：1995-12-12

申请人： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

发明人： Jean Calvignac ,  Daniel Orsatti ,  Fabrice Verplanken

IPC分类号： H04Q3/00 ,  H04L12/56

CPC分类号： H04L12/5602 ,  H04L47/10 ,  H04L49/3081 ,  H04L2012/5619 ,  H04L2012/5635 ,  H04L2012/5679

摘要： A flow control apparatus implemented in a virtual path ATM communication system comprising a plurality of nodes interconnected by physical links which comprise virtual paths including a plurality of virtual channels. A connection between two nodes is defined as the combination of a physical link, a virtual path, and a virtual channel. Connections are shared between a reserved bandwidth service and a best effort service. ATM data cells conveyed on said best effort service are routed from node to node by analyzing their virtual connection identifier. Queues, allocated as needed from a pool of free queues, are used to store all incoming ATM data cells having the same virtual channel identifier.

摘要翻译： 一种在虚拟路径ATM通信系统中实现的流控制装置，包括由包括多个虚拟信道的虚拟路径的物理链路互连的多个节点。 两个节点之间的连接被定义为物理链路，虚拟路径和虚拟信道的组合。 连接在保留的带宽服务和尽力而为的服务之间共享。 通过分析其虚拟连接标识符，在所述尽力服务上传送的ATM数据单元从节点路由到节点。 根据需要从空闲队列池分配的队列用于存储具有相同虚拟信道标识符的所有传入ATM数据单元。

公开(公告)号：US5572697A

公开(公告)日：1996-11-05

申请号：US992314

申请日：1992-12-21

申请人： Denis Chevalier ,  Jean Calvignac ,  Jean-Marie Munier ,  Bernard Naudin ,  Maurice Duault

发明人： Denis Chevalier ,  Jean Calvignac ,  Jean-Marie Munier ,  Bernard Naudin ,  Maurice Duault

IPC分类号： G06F11/00 ,  G06F5/06 ,  G06F13/00 ,  G06F15/167

CPC分类号： G06F15/167 ,  G06F5/06 ,  G06F2205/064

摘要： Apparatus for recovering lost buffer contents in a data processing system uses a memory divided into a plurality of buffers provided with buffer control blocks, through which source and destination users exchange information. A buffer management circuit is responsive to requests from users for allocating buffers to source users in order that source users may store the information to be sent to the destination users. This circuit builds buffer queues and dequeues buffers from the queues to send the information contained therein to the destination users and releases the buffers afterwards. A time mark register is settable to n different values in a predetermined order. The value of the time mark register is changed at the expiration of a time period P. Each time a buffer is allocated to one user, the current value of the time mark register is written into a time mark field of the buffer control block and a state field is set to a first value (leased). When the buffer is released, the state field is set to a second value (released). The contents of the buffer control blocks are read at regular time intervals t after period P, and the state field of every buffer control block is tested to determine whether it is set to the second value. If not so set, the time mark field is compared with the value the time mark register had at the time t-xP, where x is a number such as 1

摘要翻译： 用于恢复数据处理系统中的丢失缓冲器内容的装置使用分配有缓冲器控制块的多个缓冲器的存储器，源和目的地用户通过该缓冲器控制块交换信息。 缓冲器管理电路响应于用户向源用户分配缓冲区的请求，以便源用户可以存储要发送到目的地用户的信息。 此电路构建缓冲区队列，并从队列中将缓冲区从队列中出发，将其中包含的信息发送到目标用户，然后释放缓冲区。 时间标记寄存器可按预定顺序设置为n个不同的值。 时间标记寄存器的值在时间段P的期满时被改变。每当向一个用户分配缓冲器时，时间标记寄存器的当前值被写入缓冲器控制块的时间标记字段，并且 状态字段设置为第一个值（租用）。 当释放缓冲区时，状态字段被设置为第二个值（已释放）。 在周期P之后以规则的时间间隔t读取缓冲器控制块的内容，并且测试每个缓冲器控制块的状态字段以确定其是否被设置为第二值。 如果不设置，则时间标记字段与时间标记寄存器在时间t-xP处具有的值进行比较，其中x是诸如1

公开(公告)号：US5467359A

公开(公告)日：1995-11-14

申请号：US24061

申请日：1993-03-01

申请人： Pierre J. Huon ,  Philippe Jachimcsyk ,  Gerard Barucchi ,  Jean Calvignac ,  Fabrice Verplanken

发明人： Pierre J. Huon ,  Philippe Jachimcsyk ,  Gerard Barucchi ,  Jean Calvignac ,  Fabrice Verplanken

IPC分类号： G06F11/10 ,  G06F13/00 ,  H03M13/00 ,  H04L1/00

CPC分类号： H04L1/0057 ,  H04L1/0041 ,  H04L2001/0094

摘要： An error correction apparatus includes an error control circuit which computes for each burst of a message (for a destination unit) an error correction code as a function of an initial error correction code at the first burst of the message or of the error correction code of the previous burst and of the data bytes of the burst. The burst error correction code is sent on a medium which is separate from the data transport medium as a companion of the burst. Also, the error control circuit receives the burst error correction code from an origin unit and generates the burst error correction code to be compared with the received burst error correction code. If a mismatch is detected, the burst found in error is flagged.

摘要翻译： 纠错装置包括：错误控制电路，用于根据消息的第一个突发或者纠错码的初始纠错码，对消息的每个突发（对于目的地单元）计算纠错码，作为初始纠错码的函数 先前的突发和突发的数据字节。 突发纠错码在与数据传输介质分离的介质上发送，作为突发的伴侣。 此外，误差控制电路从原点单元接收脉冲串纠错码，并产生与接收脉冲串纠错码进行比较的脉冲串纠错码。 如果检测到不匹配，则会发现错误中发现的突发状况。

公开(公告)号：US5134636A

公开(公告)日：1992-07-28

申请号：US657906

申请日：1991-02-20

申请人： Gerard Barucchi ,  Jean Calvignac ,  Jose Galcera ,  Gilles Toubol ,  Andre Tracol ,  Daniel Orsatti

发明人： Gerard Barucchi ,  Jean Calvignac ,  Jose Galcera ,  Gilles Toubol ,  Andre Tracol ,  Daniel Orsatti

IPC分类号： G06F1/12 ,  H03L7/06 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0629

摘要： The synchronization circuit resynchronizes the data bits received from remote devices on line or link (20-1) with their own clock CS and frame synchronization signal FS with a central clock CO and central frame synchronization signal FO. The received bits are sequentially arranged in an n-bit cyclic buffer (114-1) with the received bit clock CS. The arranged bits are sequentially picked at the opposite buffer position with the central clock CO. The buffer loading position is provided by binary counter 102 incremented by CS and the buffer picking portion is given by binary counter 100 incremented by CO. At initialization counters 102 and 100 are set to 0 and n/2. The resynchronized data bits on line 21-1 and the resynchronized frame signal FSR on line 61-10 are provided to an additional circuit which synchronize the data bits at the frame level.

公开(公告)号：US4761781A

公开(公告)日：1988-08-02

申请号：US893075

申请日：1986-08-04

申请人： Jean Calvignac ,  Pierre Secondo

发明人： Jean Calvignac ,  Pierre Secondo

IPC分类号： H04J3/16 ,  H04L12/64 ,  H04J3/26

CPC分类号： H04J3/1629 ,  H04L12/64

摘要： Method and system for configuring a succession of complex frames to be used for exchanging synchronous circuit switched bits and asynchronous packet switched bits between nodes connected through medium links working at any bit rates in a teleprocessing network. Each complex frame contains an integer number of bits equal to Nc or Nc+1 chosen as close as possible to a predetermined number Na (256) and concludes a succession of subframes delimited by flags, in such a way that the period between two flags is equal to nT+e, T being the period of existing Time Divison Multiplex Frames (125 microseconds) and n being an integer number equal to or greater than 1 which depends upon the medium link bit rate and e being a period of time lower than a medium link bit period. The subframes have a duration equal to or less than T, each subframe containing an integer number of bits Nsi, said integer number being allocated to carry an integer number of circuit switched bit slots and the remaining bits being dedicated to asynchronous packet switched bits. The R bits remaining in the complex frame, with ##EQU1## are used for flag bits f and r=R-f bits are used for asynchronous packet switched bits.

摘要翻译： 用于配置一系列复杂帧的方法和系统，用于在通过在远程处理网络中以任何比特率工作的介质链路连接的节点之间交换同步电路交换位和异步分组交换位。 每个复帧包含等于Nc或Nc + 1的整数位，尽可能地选择为接近预定数目Na（256），并且以由两个标志之间的周期来确定由标志分隔的一系列子帧 等于nT + e，T是现有时分多路复用帧（125微秒）的周期，n是等于或大于1的整数，这取决于中链路比特率，e是低于 中链路位周期。 子帧具有等于或小于T的持续时间，每个子帧包含整数个比特数Nsi，所述整数被分配以携带整数个电路交换比特时隙，其余比特专用于异步分组交换比特。 残留在复帧中的R位与用于标志位f，r = R-f位用于异步分组交换位。

公开(公告)号：US20080107038A1

公开(公告)日：2008-05-08

申请号：US11970868

申请日：2008-01-08

申请人： James Allen ,  Jean Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

发明人： James Allen ,  Jean Calvignac ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken

IPC分类号： G06F11/30

CPC分类号： H04L1/0061 ,  H04L1/0072 ,  H04L12/5601 ,  H04L45/742 ,  H04L2012/5627 ,  H04L2012/5656

摘要： The CRC for the CPS Header of an ATM AAL2 cell is generated by a CRC generator which uses the 8 bits of the CID field to generate partial 5 bits CRCs which are loaded in a first table. The 6 bits LI field and 5 bits UUI field are added to the partial 5 bits CRC to form 16 bits. The CRC generator uses the 2.sup.16 bits to generate a second CRC table. The CRC for a particular CPS header is generated by correlating bits in the CID field, LI field and UUI field with the two tables.

公开(公告)号：US20070294471A1

公开(公告)日：2007-12-20

申请号：US11832220

申请日：2007-08-01

申请人： Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

发明人： Jean Calvignac ,  Chih-jen Chang ,  Gordon Davis ,  Fabrice Verplanken

IPC分类号： G06F12/00

CPC分类号： G06F13/1642

摘要： Access arbiters are used to prioritize read and write access requests to individual memory banks in DRAM memory devices, particularly fast cycle DRAMs. This serves to optimize the memory bandwidth available for the read and the write operations by avoiding consecutive accesses to the same memory bank and by minimizing dead cycles. The arbiter first divides DRAM accesses into write accesses and read accesses. The access requests are divided into accesses per memory bank with a threshold limit imposed on the number of accesses to each memory bank. The write receive packets are rotated among the banks based on the write queue status. The status of the write queue for each memory bank may also be used for system flow control. The arbiter also typically includes the ability to determine access windows based on the status of the command queues, and to perform arbitration on each access window.

摘要翻译： 访问仲裁器被用于将对DRAM存储器件，特别是快速循环DRAM中的各个存储体的读取和写入访问请求进行优先级排序。 这用于通过避免对同一存储体的连续访问并且通过最小化死循环来优化用于读取和写入操作的存储器带宽。 仲裁器首先将DRAM访问划分为写访问和读访问。 访问请求被划分为每个存储体的访问，并且对每个存储体的访问次数施加了阈值限制。 基于写入队列状态，写入接收数据包在存储体之间旋转。 每个存储体的写入队列的状态也可以用于系统流控制。 仲裁器还通常包括基于命令队列的状态来确定访问窗口的能力，并且在每个访问窗口上执行仲裁。

公开(公告)号：US20060285551A1

公开(公告)日：2006-12-21

申请号：US11467848

申请日：2006-08-28

申请人： Kenneth Barker ,  Rolf Clauberg ,  Jean Calvignac ,  Andreas Herkersdorf ,  Fabrice Verplanken ,  David Webb

发明人： Kenneth Barker ,  Rolf Clauberg ,  Jean Calvignac ,  Andreas Herkersdorf ,  Fabrice Verplanken ,  David Webb

IPC分类号： H04J3/22

CPC分类号： H04J3/1611 ,  H04J3/0685 ,  H04J3/22 ,  H04J2203/0089

摘要： The present invention relates to a device for combining at least two data signals having an input data rate into a single data stream having an output data rate being higher than the input data rate for transmission on a shared medium or vice versa, particularly, to a single SDH/SONET framer capable of handling a large range of SDH/SONET frames from STM-i to STM-j with an aggregated total capacity corresponding to an STM-j frame where i and j are integers in the range from 1 to 64 or higher according to the STM-N definition of the SDH/SONET standards. More over, the present invention can also be extended to work with STS-1 as lowest range. STS-1 exists in SONET only not SDH and corresponds to a data rate of 51.5 Mb/s a third of the 156 Mb/s of STM-1. The device according to the present invention comprises at least two ports for receiving and/or sending said at least two data signals, a port snning unit for extracting data from the data signals received by said ports and/or synthesizing data to be transmitted via the ports, respectively, whereby said port scanning unit is configured to extract data from ports providing data streams having at least two different input data rates and/or to synthesize data to be transmitted via the ports taking data streams having at least two different data rates.

摘要翻译： 本发明涉及一种用于将具有输入数据速率的至少两个数据信号组合成具有高于用于在共享介质上传输的输入数据速率的输出数据速率的单个数据流的装置，反之亦然，特别涉及一种 单个SDH / SONET成帧器能够处理从STM-i到STM-j的大范围的SDH / SONET帧，具有对应于STM-j帧的聚合总容量，其中i和j是从1到64的整数或 根据SDH / SONET标准的STM-N定义更高。 更进一步地，本发明也可以扩展到使用STS-1作为最低范围。 STS-1仅存在于SONET中而不是SDH，对应于156Mb / s的STM-1的三分之一的51.5Mb / s的数据速率。 根据本发明的装置包括用于接收和/或发送所述至少两个数据信号的至少两个端口，用于从由所述端口接收的数据信号中提取数据和/或合成要通过所述端口发送的数据的端口捕捉单元 其中所述端口扫描单元被配置为从提供具有至少两个不同输入数据速率的数据流的端口提取数据和/或合成要通过端口发送的数据，该数据流具有至少两个不同数据速率的数据流。

公开(公告)号：US20060265363A1

公开(公告)日：2006-11-23

申请号：US11457952

申请日：2006-07-17

申请人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

发明人： Jean Calvignac ,  Gordon Davis ,  Marco Heddes ,  Michael Siegel

IPC分类号： G06F17/30

CPC分类号： H04L49/3009 ,  G11C15/00 ,  H04L45/745 ,  H04L45/7453 ,  H04L49/90

摘要： A method and system for identifying a data structure associated with a packet of data. A processor internal to a packet processor may extract one or more fields in a packet header field of a received packet of data to generate a search key. The internal processor may then be configured to select which table, e.g., routing table, quality of service table, filter table, needs to be accessed using the search key in order to process the received packet of data. A determination may then be made by the internal processor as to whether a CAM or a hash table and a Patricia Tree are used to identify the data structure associated with the received packet of data. Based on table definitions in a register, the internal processor may make such a determination.

摘要翻译： 一种用于识别与数据包相关联的数据结构的方法和系统。 分组处理器内部的处理器可以提取接收到的数据分组的分组报头字段中的一个或多个字段以生成搜索关键字。 然后可以将内部处理器配置为选择哪个表，例如路由表，服务质量表，过滤表，需要使用搜索关键字进行访问，以便处理接收的数据分组。 然后内部处理器可以确定CAM或散列表和Patricia Tree是否用于标识与所接收的数据分组相关联的数据结构。 根据寄存器中的表定义，内部处理器可以作出这样的确定。

公开(公告)号：US20060221953A1

公开(公告)日：2006-10-05

申请号：US11097055

申请日：2005-04-01

申请人： Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Ronald Fuhs ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli ,  Scott Willenborg

发明人： Claude Basso ,  Jean Calvignac ,  Chih-Jen Chang ,  Philippe Damon ,  Ronald Fuhs ,  Natarajan Vaidhyanathan ,  Fabrice Verplanken ,  Colin Verrilli ,  Scott Willenborg

IPC分类号： H04L12/56 ,  H04L12/28

CPC分类号： H04L69/16 ,  H04L1/0041 ,  H04L1/0061 ,  H04L1/0072 ,  H04L69/161

摘要： Method and apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.

摘要翻译： 用于在网络传输中提供校验和的方法和装置。 在本发明的一个方面，通过从存储设备检索分组信息来确定要在网络上发送的分组的校验和，所述分组信息将包括在要发送的分组中。 基于检索的分组信息确定盲校验和值，并且基于描述分组的结构的描述符信息将盲校验和值调整为协议校验和。 在分组发送之前，协议校验和被插入到分组中。