公开(公告)号：US20100111034A1

公开(公告)日：2010-05-06

申请号：US12264454

申请日：2008-11-04

申请人： Vinko Erceg ,  Arya Reza Behzad ,  David John Rosmann ,  Brima B. Ibrahim ,  Jeyhan Karaoguz ,  John Walley

发明人： Vinko Erceg ,  Arya Reza Behzad ,  David John Rosmann ,  Brima B. Ibrahim ,  Jeyhan Karaoguz ,  John Walley

IPC分类号： H04W36/00

CPC分类号： H04W36/28

摘要： A management unit allocates network resources to a plurality of multiservice communication devices capable of communicating via a plurality of networks. The management unit includes a communication device interface for facilitating a bidirectional data communication with the plurality of multiservice communication devices via a wireless control channel, the bidirectional data communication including outbound control data sent to at least one of the plurality of multiservice communication devices and inbound control data received from at least one of the plurality of multiservice communication devices, wherein the wireless control channel is separate from the communication between the plurality of multiservice communication devices and the plurality of networks. A network interface receives network resource data from the plurality of networks. A management processing unit generates the outbound control data in response thereto, wherein the management processing unit facilities the handoff of a real-time service accessed by the at least one of the plurality of multiservice communication devices via a first network of the plurality of networks to a second network of the plurality of networks.

摘要翻译： 管理单元将网络资源分配给能够经由多个网络进行通信的多个多业务通信设备。 管理单元包括通信设备接口，用于经由无线控制信道促进与多个多业务通信设备的双向数据通信，所述双向数据通信包括发送到多个多业务通信设备中的至少一个的出站控制数据和入站控制 从所述多个多业务通信设备中的至少一个接收的数据，其中所述无线控制信道与所述多个多业务通信设备和所述多个网络之间的通信分离。 网络接口从多个网络接收网络资源数据。 管理处理单元响应于此生成出站控制数据，其中管理处理单元将由多个多服务通信设备中的至少一个访问的实时服务经由多个网络的第一网络切换到 所述多个网络的第二网络。

公开(公告)号：US20100016004A1

公开(公告)日：2010-01-21

申请号：US12569885

申请日：2009-09-29

申请人： Arya Reza Behzad

发明人： Arya Reza Behzad

IPC分类号： H04B7/00

CPC分类号： H04B1/0082 ,  H04B7/00 ,  H04B17/14

摘要： A Radio Frequency (RF) transceiver includes a first RF transceiver group, a second RF transceiver group, local oscillation circuitry, and calibration control circuitry. Each of the RF transceiver group has an RF transmitter and an RF receiver. The local oscillation circuitry selectively produces a local oscillation to the first RF transceiver group and to the second RF transceiver group. The calibration control circuitry is operable to initiate calibration operations including transmitter self calibration operations, first loopback calibration operations, and second loopback calibration operations. During loopback calibration operations, test signals produced by an RF transceiver group are looped back to an RF receiver of another RF transceiver group.

摘要翻译： 射频（RF）收发器包括第一RF收发器组，第二RF收发器组，本地振荡电路和校准控制电路。 RF收发器组中的每一个具有RF发射器和RF接收器。 本地振荡电路选择性地向第一RF收发机组和第二RF收发机组产生本地振荡。 校准控制电路可操作以启动校准操作，包括发射器自校准操作，第一回送校准操作和第二回送校准操作。 在环回校准操作期间，由RF收发器组产生的测试信号被环回到另一RF收发器组的RF接收器。

公开(公告)号：US20090124219A1

公开(公告)日：2009-05-14

申请号：US12181572

申请日：2008-07-29

申请人： Arya Reza Behzad

发明人： Arya Reza Behzad

IPC分类号： H04B17/00

CPC分类号： H03F3/45179 ,  H03F1/02 ,  H03F1/0261 ,  H03F1/08 ,  H03F1/32 ,  H03F1/3211 ,  H03F3/24 ,  H03F3/45188 ,  H03F2200/372 ,  H04B1/0475 ,  H04B2001/045

摘要： A communications transceiver includes a baseband processor, a receiver section, and a transmitter section that includes a power amplifier. The receiver and transmitter sections communicatively couple to the baseband processor. In a calibration operation, the baseband processor produces a test signal to the transmitter section. Further, the baseband processor causes each of a plurality of power amplifier bias settings to be applied to the power amplifier. For each of the plurality of power amplifier bias settings, the power amplifier produces an amplified test signal, the receiver section couples back a portion of the amplified test signal to the baseband processor, and the baseband processor produces a characterization of the amplified test signal respective. Based upon a plurality of characterizations of the amplified test signal and respective power amplifier bias settings, the baseband processor determines power amplifier bias control settings. The baseband processor then applies the power amplifier bias control settings to the power amplifier.

摘要翻译： 通信收发器包括基带处理器，接收器部分和包括功率放大器的发射器部分。 接收机和发射机部分通信地耦合到基带处理器。 在校准操作中，基带处理器向发射机部分产生测试信号。 此外，基带处理器使得多个功率放大器偏置设置中的每一个被施加到功率放大器。 对于多个功率放大器偏置设置中的每一个，功率放大器产生放大的测试信号，接收器部分将放大的测试信号的一部分耦合到基带处理器，并且基带处理器产生放大的测试信号的表征 。 基于放大的测试信号和各个功率放大器偏置设置的多个表征，基带处理器确定功率放大器偏置控制设置。 然后，基带处理器将功率放大器偏置控制设置应用于功率放大器。

公开(公告)号：US07340220B2

公开(公告)日：2008-03-04

申请号：US11184423

申请日：2005-07-19

申请人： Arya Reza Behzad ,  Hung-Ming Ed Chien

发明人： Arya Reza Behzad ,  Hung-Ming Ed Chien

IPC分类号： H04B1/40

CPC分类号： H03L7/18 ,  H03L7/0802 ,  H03L7/0891

摘要： A phase locked loop includes a detection module, a control conversion module, a controlled oscillation module, a divider module, and a power distribution module. The detection module is operably coupled to produce a difference signal based on a difference between a reference oscillation and a feedback oscillation. The control conversion module is operably coupled to convert the difference signal into a control signal. The controlled oscillation module is operably coupled to produce an output oscillation based on the control signal. The divider module is operably coupled to produce the feedback oscillation based on the output oscillation. The power distribution module is operably coupled to receive a supply voltage and to provide an individual supply voltage to at least one of the detection module, the control conversion module, the controlled oscillation module, and the divider module to optimize at least one of performance and power consumption of the phase locked loop.

摘要翻译： 锁相环包括检测模块，控制转换模块，受控振荡模块，分频模块和配电模块。 检测模块可操作地耦合以基于参考振荡和反馈振荡之间的差产生差分信号。 控制转换模块可操作地耦合以将差分信号转换成控制信号。 受控振荡模块可操作地耦合以基于控制信号产生输出振荡。 分压器模块可操作地耦合以基于输出振荡产生反馈振荡。 功率分配模块可操作地耦合以接收电源电压并且向检测模块，控制转换模块，受控振荡模块和分频器模块中的至少一个提供单独的电源电压，以优化性能和 锁相环的功耗。

公开(公告)号：US20080025380A1

公开(公告)日：2008-01-31

申请号：US11800208

申请日：2007-05-04

申请人： Arya Reza Behzad ,  Mark Gonikberg ,  Ahmadreza (Raza) Rofougaran

发明人： Arya Reza Behzad ,  Mark Gonikberg ,  Ahmadreza (Raza) Rofougaran

IPC分类号： H04L25/00

CPC分类号： H04B15/02 ,  H04B15/06 ,  H04B2215/064 ,  H04B2215/068 ,  H04L27/0014 ,  Y02D70/122 ,  Y02D70/124

摘要： An integrated circuit (IC) includes a clock circuit, a processing module, and processing circuitry. The clock circuit is coupled to produce a digital clock signal. The processing module is coupled to determine whether a harmonic component of the digital clock signal having a nominal digital clock rate is within the frequency passband and to provide an indication to the clock circuit to adjust its rate from the nominal digital clock rate to an adjusted digital clock rate when the harmonic component of the digital clock signal is within the frequency passband. The processing circuitry is coupled to process, at the adjusted digital clock rate, the data to produce processed data having a rate corresponding to the nominal digital clock rate and to interpolate, at an interpolation rate, the processed data to produce interpolated processed data having a rate corresponding to the interpolation rate.

摘要翻译： 集成电路（IC）包括时钟电路，处理模块和处理电路。 时钟电路被耦合以产生数字时钟信号。 处理模块被耦合以确定具有标称数字时钟速率的数字时钟信号的谐波分量是否在频带内，并且向时钟电路提供指示以将其速率从标称数字时钟速率调整到调整数字 数字时钟信号的谐波分量在频带内的时钟频率。 处理电路被耦合以以调整的数字时钟速率处理数据以产生具有对应于标称数字时钟速率的速率的处理数据，并且以内插速率内插处理后的数据以产生经内插处理的数据，其具有 速率对应于插补率。

公开(公告)号：US07212586B2

公开(公告)日：2007-05-01

申请号：US10052870

申请日：2002-01-18

申请人： Zhongming Shi ,  Reza Rofougaran ,  Arya Reza Behzad

发明人： Zhongming Shi ,  Reza Rofougaran ,  Arya Reza Behzad

IPC分类号： H03K9/00 ,  H04L27/16

CPC分类号： H03G3/3042 ,  H03J7/04 ,  H04B1/04 ,  H04B1/30 ,  H04B1/408 ,  H04B2001/0416

摘要： A single chip radio transceiver includes circuitry that enables received wideband RF signals to be down converted to base band frequencies and base band signals to be up converted to wideband RF signals prior to transmission without requiring conversion to an intermediate frequency. The circuitry includes a low noise amplifier, automatic frequency control circuitry for aligning the LO frequency with the frequency of the received RF signals, signal power measuring circuitry for measuring the signal to signal and power ratio and for adjusting frontal and rear amplification stages accordingly, and finally, filtering circuitry to filter high and low frequency interfering signals including DC offset.

摘要翻译： 单芯片无线电收发机包括使接收的宽带RF信号下变频到基带频率和基带信号在传输之前被上转换成宽带RF信号的电路，而不需要转换到中频。 该电路包括一个低噪声放大器，自动频率控制电路，用于将LO频率与接收到的RF信号的频率对准，信号功率测量电路，用于测量信号与信号和功率比，并相应地调整正面和后置放大级;以及 最后，滤波电路对高频和低频干扰信号进行滤波，包括直流偏移。

公开(公告)号：US07173505B2

公开(公告)日：2007-02-06

申请号：US10842825

申请日：2004-05-11

申请人： Arya Reza Behzad

发明人： Arya Reza Behzad

IPC分类号： H03J5/24

CPC分类号： H03D7/1441 ,  H01L2223/6611 ,  H03D7/1458 ,  H03D7/1483 ,  H03D2200/0043 ,  H03F1/565 ,  H03F3/191 ,  H03F3/45188 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45638 ,  H03F2203/45704 ,  H03F2203/45726 ,  H03F2203/45728 ,  H03F2203/7209 ,  H03J5/244 ,  H03J2200/10

摘要： A Radio Frequency (RF) circuit includes an active portion and a tuned portion. The active portion receives an RF signal and that operates upon the RF signal. The tuned portion couples to the active portion and includes a first inductor, a second inductor, and a switch. When the switch is closed, the second inductor couples to the first inductor and the tuned portion has first tuning characteristics. When the switch is open, the second inductor is decoupled from the first inductor and the tuned portion has second tuning characteristics. The tuned portion may include lumped or parasitic capacitance. The tuned portion alternately includes an inductor having a first terminal, a second terminal, an intermediate tap, and a switch that couples between the second terminal and the intermediate tap. When the switch is closed the tuned portion has first tuning characteristics and when the switch is open, the tuned portion has second tuning characteristics.

摘要翻译： 射频（RF）电路包括有源部分和调谐部分。 有源部分接收RF信号，并且根据RF信号进行操作。 调谐部分耦合到有源部分并且包括第一电感器，第二电感器和开关。 当开关闭合时，第二电感器耦合到第一电感器，并且调谐部分具有第一调谐特性。 当开关断开时，第二电感器与第一电感器分离，调谐部分具有第二调谐特性。 调谐部分可以包括集总或寄生电容。 调谐部分交替地包括具有第一端子，第二端子，中间抽头以及耦合在第二端子和中间抽头之间的开关的电感器。 当开关闭合时，调谐部分具有第一调谐特性，并且当开关断开时，调谐部分具有第二调谐特性。

公开(公告)号：US07129589B2

公开(公告)日：2006-10-31

申请号：US10971506

申请日：2004-10-22

申请人： Arya Reza Behzad

发明人： Arya Reza Behzad

IPC分类号： H01L23/62 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L27/0255 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/50 ,  H01L23/60 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6611 ,  H01L2224/32188 ,  H01L2224/48091 ,  H01L2224/48237 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A circuit includes a plurality of circuit components formed on a semi conductive substrate die and a bond wire. The plurality of circuit components include at least one active component that operates on an information signal, a tuning node coupled to the at least one active component, an Electro Static Discharge (ESD) protection inductor, and a chip pad. The chip pad couples to the tuning node. The ESD protection inductor communicatively couples between the tuning node and a rail formed on the semi conductive substrate die. The ESD protection inductor provides ESD protection prior to packaging of the semi conductive substrate die or in some cases prior to the installation of the packaged die on a PC board or the equivalent. The bond wire couples between the chip pad and a package pad and serves as a tuning inductor for the circuit.

摘要翻译： 电路包括形成在半导体基板芯片和接合线上的多个电路部件。 所述多个电路部件包括对信息信号进行操作的至少一个有源部件，耦合到所述至少一个有源部件的调谐节点，静电放电（ESD）保护电感器和芯片焊盘。 芯片焊盘耦合到调谐节点。 ESD保护电感器在调谐节点和形成在半导电衬底裸片上的导轨之间通信地耦合。 ESD保护电感器在封装半导体衬底裸片之前或在某些情况下，在将封装的裸片安装在PC板或等效电路之前提供ESD保护。 接合线耦合在芯片焊盘和封装焊盘之间，并用作电路的调谐电感器。

公开(公告)号：US07106122B2

公开(公告)日：2006-09-12

申请号：US11087662

申请日：2005-03-24

申请人： Arya Reza Behzad

发明人： Arya Reza Behzad

IPC分类号： G11B5/02

CPC分类号： H03G1/0088 ,  H03G3/001 ,  H03G3/3036

摘要： An apparatus for providing a programmable gain attenuator (PGA) while minimizing the influence of semiconductor switches on the signal being attenuated. An example apparatus comprises a impedance ladder with taps forming the junctions between impedances the PGA is then programmed by grounding the taps through terminating resistors.

摘要翻译： 一种用于提供可编程增益衰减器（PGA）的设备，同时最小化半导体开关对被衰减的信号的影响。 示例性装置包括阻抗梯形图，其中抽头形成阻抗之间的接合点，然后通过终止电阻器将抽头接地来编程PGA。

公开(公告)号：US07081790B2

公开(公告)日：2006-07-25

申请号：US11087594

申请日：2005-03-24

申请人： Arya Reza Behzad

发明人： Arya Reza Behzad

IPC分类号： H03K5/00

CPC分类号： H03G5/10 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03H11/245

摘要： Often programmable gain attenuators (PGAs) are combined with high pass filters. Adjustment of the highpass filter however can have unintended effects, such as changing the step size of the PGA. By placing the resistance of the highpass filter in parallel with a programmable attenuator divider, the steps of the PGA can be minimally affected as the highpass frequency is adjusted.

摘要翻译： 通常可编程增益衰减器（PGA）与高通滤波器组合。 然而，高通滤波器的调整可能会产生意想不到的影响，例如改变PGA的步长。 通过将高通滤波器的电阻与可编程衰减器分压器并联，PGA的步骤可以在高通滤波器调整时受到最小的影响。