公开(公告)号：US20060226868A1

公开(公告)日：2006-10-12

申请号：US11402123

申请日：2006-04-11

申请人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

发明人： Woo-Jin Lee ,  Kwang-Il Park ,  Hyun-Jin Kim ,  Seong-Jin Jang

IPC分类号： H03K19/003

CPC分类号： H03K19/0005

摘要： Provided is a semiconductor device capable of controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a control method used by the semiconductor device. The semiconductor device includes a control code generation unit generating a control code in response to a control signal, an addition unit adding an adjustment code to the control code to produce an adjusted control code, and an ODT circuit, wherein an impedance of the ODT circuit is adjusted in response to the adjusted control code. The semiconductor device can adjust the control code more precisely by adding or subtracting the adjustment code to or from the control code. Accordingly, the impedance of an OCD circuit or ODT circuit can be adjusted more precisely.

摘要翻译： 提供了能够控制芯片上终端（ODT）电路和芯片外驱动器（OCD）电路的半导体器件以及由半导体器件使用的控制方法。 半导体器件包括响应于控制信号产生控制代码的控制代码生成单元，向控制代码添加调整代码以产生调整后的控制代码的加法单元和ODT电路，其中ODT电路的阻抗 根据调整后的控制代码进行调整。 半导体器件可以通过向或从控制代码添加或减去调整代码来更精确地调整控制代码。 因此，可以更精确地调整OCD电路或ODT电路的阻抗。

公开(公告)号：US20060066364A1

公开(公告)日：2006-03-30

申请号：US11225915

申请日：2005-09-13

申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-Il Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

IPC分类号： H03B1/00

CPC分类号： H03F3/45

摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

摘要翻译： 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括：第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。

公开(公告)号：US20050174858A1

公开(公告)日：2005-08-11

申请号：US11024272

申请日：2004-12-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C11/407 ,  G11C5/00 ,  G11C7/22 ,  G11C11/40 ,  G11C11/409

CPC分类号： G11C7/22 ,  G11C7/1066

摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。 与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

公开(公告)号：US06850110B2

公开(公告)日：2005-02-01

申请号：US10108276

申请日：2002-03-27

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C5/14 ,  H02M3/07 ,  G06F7/64

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A voltage generating circuit and method thereof for preventing a current from flowing from a voltage generating node to a pumping node in transiting of the circuit from an active operation to a pre-charge operation are provided. The voltage generating circuit comprises a pre-charge circuit for pre-charging a pumping node and a voltage transmitting control node during a pre-charge operation; a voltage pumping circuit for pumping a signal at the pumping node during an active operation; a voltage transmitting circuit for transmitting the signal from the pumping node to a voltage generating node in response to a signal at the voltage transmitting control node during the active operation; and a countercurrent preventing circuit for varying the signal at the voltage transmitting control node based on the signal at the pumping node during the pre-charge operation and for preventing a current from flowing between the pumping node and the voltage transmitting control node during the active operation.

摘要翻译： 提供一种电压产生电路及其方法，用于防止电流从电压产生节点流向泵送节点，以将电路从有源操作转移到预充电操作。 电压产生电路包括用于在预充电操作期间预充电泵浦节点和电压发送控制节点的预充电电路; 用于在主动操作期间泵送泵送节点处的信号的电压泵浦电路; 电压发送电路，用于在主动操作期间响应于电压发送控制节点处的信号将信号从泵送节点发送到电压产生节点; 以及逆流防止电路，用于在预充电操作期间基于泵送节点处的信号来改变电压发送控制节点处的信号，并且用于在主动操作期间防止在泵送节点和电压发送控制节点之间流动的电流 。

公开(公告)号：US20050005054A1

公开(公告)日：2005-01-06

申请号：US10737861

申请日：2003-12-18

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F12/04 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C7/1006 ,  G11C7/1051 ,  G11C7/1063 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1096

摘要： A memory system and a method of reading and writing data to a memory device provide byte-by-byte write data insertion without adding extra pins or balls to the packaged device. Accordingly, the high frequency performance of the device can be improved.

摘要翻译： 存储器系统和将数据读取和写入存储器件的方法提供逐字节写入数据插入，而不会向封装器件添加额外的引脚或球。 因此，可以提高装置的高频性能。

公开(公告)号：US20050005053A1

公开(公告)日：2005-01-06

申请号：US10733413

申请日：2003-12-12

申请人： Seong-Jin Jang

发明人： Seong-Jin Jang

IPC分类号： G11C11/407 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401

CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C7/1075

摘要： A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

摘要翻译： 存储器系统和将数据读取和写入到存储器件的方法选择性地在具有数据反转的单个DQS模式中操作，并且以双DQS模式操作。 该装置和方法采用数据选通模式改变装置，用于在第一数据选通模式和第二数据选通模式之间选择性地改变存储装置的操作。

公开(公告)号：US06788132B2

公开(公告)日：2004-09-07

申请号：US10147553

申请日：2002-05-17

申请人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

发明人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

IPC分类号： G05F302

CPC分类号： G05F1/465

摘要： Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

摘要翻译： 提供了集成电路，其包括电压控制电路，其被配置为将预定电路电压规范之外的电路电压调整到预定电路电压规范内，使得集成电路器件不再有缺陷。 还提供了集成电路，其包括信号时间延迟控制电路，其被配置为将预定电路延迟时间规范之外的电路延迟时间调整到预定电路延迟时间规范内，使得集成电路装置不再有缺陷。 还提供了相应的操作方法。

公开(公告)号：US08780668B2

公开(公告)日：2014-07-15

申请号：US13483719

申请日：2012-05-30

申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。

公开(公告)号：US08483001B2

公开(公告)日：2013-07-09

申请号：US13612514

申请日：2012-09-12

申请人： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

发明人： Ki-Heung Kim ,  Yong-Ho Cho ,  Ji-Hoon Lim ,  Seong-Jin Jang ,  Tae-Yoon Lee

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G01R19/16552 ,  G11C5/147 ,  H03K5/2481

摘要： A level detector, an internal voltage generator including the level detector, and a semiconductor memory device including the internal voltage generator are provided. The internal voltage generator includes a level detector that compares a threshold voltage that varies with temperature with an internal voltage to output a comparative voltage, and an internal voltage driver that adjusts an external supply voltage in response to the comparative voltage and that outputs an internal voltage.

摘要翻译： 提供了一种电平检测器，包括电平检测器的内部电压发生器和包括内部电压发生器的半导体存储器件。 内部电压发生器包括电平检测器，其将与温度变化的阈值电压与内部电压进行比较以输出比较电压;以及内部电压驱动器，其响应于比较电压调节外部电源电压并且输出内部电压 。

公开(公告)号：US08432762B2

公开(公告)日：2013-04-30

申请号：US13006832

申请日：2011-01-14

申请人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

发明人： Joung-Yeal Kim ,  Seong-Jin Jang ,  Jin-Seok Kwak

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： A bitline sense amplifier includes a pre-sensing unit and an amplification unit. The pre-sensing unit is connected to a first bitline and a second bitline, and is configured to perform a pre-sensing operation by controlling a voltage level of the second bitline based on at least one pre-sensing voltage and variation of a voltage level of the first bitline. The amplification unit is configured to perform a main amplification operation by amplifying a pre-sensed voltage difference based on a first voltage signal and a second voltage signal. The pre-sensed voltage difference indicates a difference between the voltage level of the first bitline and the voltage level of the second bitline after the pre-sensing operation.

摘要翻译： 位线读出放大器包括预感测单元和放大单元。 预感测单元连接到第一位线和第二位线，并且被配置为通过基于至少一个预感测电压和电压电平的变化来控制第二位线的电压电平来执行预感测操作 的第一个位线。 放大单元被配置为通过基于第一电压信号和第二电压信号放大预感测电压差来执行主放大操作。 预感测电压差表示在预感测操作之后第一位线的电压电平和第二位线的电压电平之间的差。