公开(公告)号：US06194954B1

公开(公告)日：2001-02-27

申请号：US09221990

申请日：1998-12-29

申请人： Saeng-Hwan Kim ,  Kwang-Jin Lee ,  Ki-Chang Chun

发明人： Saeng-Hwan Kim ,  Kwang-Jin Lee ,  Ki-Chang Chun

IPC分类号： G05F110

CPC分类号： G05F3/205 ,  H03K3/0315

摘要： The voltage control generator for a semiconductor device is disclosed, in which the substrate bias voltage through the oscillation period of the step-up voltage generator circuit are quickly adjusted with respect to the level variation of a corresponding voltage. The circuit according to the present invention includes a control level generator generating at least one control signal for detecting a substrate bias voltage level from a substrate of a semiconductor device and adjusting the width of an oscillation period to a set level in accordance with the detected signal, a voltage control oscillator generating a signal in which the width of an oscillation period is varied to the set level in response to an output signal from the control level generator, and a charge pump supplying a stable bias voltage to the substrate of the semiconductor device by increasing or decreasing a pumping speed in response to an output signal from the voltage control oscillator. Since the voltage control oscillator is used as an oscillator for determining the pumping period of the charge pump, it is possible to effectively control the oscillation period in accordance with the detected voltage level variation for thereby decreasing the power consumption.

摘要翻译： 公开了一种用于半导体器件的电压控制发生器，其中通过升压电压发生器电路的振荡周期的衬底偏置电压相对于相应电压的电平变化被快速调节。 根据本发明的电路包括控制电平发生器，其产生用于从半导体器件的衬底检测衬底偏置电压电平的至少一个控制信号，并且根据检测到的信号将振荡周期的宽度调整到设定电平 产生振荡周期的宽度响应于来自控制电平发生器的输出信号而变化到设定电平的信号的电压控制振荡器，以及向半导体器件的衬底提供稳定的偏置电压的电荷泵 通过响应于来自电压控制振荡器的输出信号增加或减小泵送速度。 由于电压控制振荡器用作用于确定电荷泵的泵浦周期的振荡器，因此可以根据检测到的电压电平变化来有效地控制振荡周期，从而降低功耗。

公开(公告)号：US08956537B2

公开(公告)日：2015-02-17

申请号：US13258610

申请日：2010-03-23

申请人： Kwang-Jin Lee ,  Moo-Seok Lee

发明人： Kwang-Jin Lee ,  Moo-Seok Lee

IPC分类号： B01D69/08 ,  B01D63/04 ,  B01D63/02 ,  B01D65/00

CPC分类号： B01D63/02 ,  B01D63/026 ,  B01D65/00 ,  B01D2313/02 ,  B01D2313/06 ,  B01D2313/12 ,  B01D2313/21 ,  B01D2315/06 ,  Y10T29/49826

摘要： Disclosed are a hollow fiber membrane module, a filtration apparatus based on the same, and a method for manufacturing the filtration apparatus. The hollow fiber membrane module includes two headers respectively provided with a permeate collecting unit therein, wherein each of the headers has grooves on its two sides, the grooves being extended in a length direction of the hollow fiber membrane. Since one slide rod can simultaneously be inserted into grooves of two adjacent hollow fiber membrane modules, the hollow fiber membrane modules can mutually serve as guides for insertion/ejection thereof. Also, since the grooves formed on the header can serve as insertion holes into which a clamp is inserted, the clamp can be used for coupling between the hollow fiber membrane module and another element and reinforcement of the coupling.

摘要翻译： 公开了一种中空纤维膜组件，基于该过滤装置的过滤装置及其制造方法。 中空纤维膜组件包括两个头部，其中分别设置有渗透物收集单元，其中每个集管在其两侧具有凹槽，所述凹槽沿中空纤维膜的长度方向延伸。 由于一个滑杆可以同时插入两个相邻的中空纤维膜组件的槽中，所以中空纤维膜组件可以作为其插入/弹出的引导件。 此外，由于形成在集管上的槽可以用作插入夹具的插入孔，所以夹具可用于中空纤维膜组件和另一元件之间的联接以及联接器的加固。

公开(公告)号：US20140042074A1

公开(公告)日：2014-02-13

申请号：US14113307

申请日：2012-04-26

申请人： Jung-min Noh ,  Dae Joong Kim ,  Dong-eul Park ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Kwang-Jin Lee

发明人： Jung-min Noh ,  Dae Joong Kim ,  Dong-eul Park ,  Ah Reum Lee ,  Yong-Cheol Shin ,  Kwang-Jin Lee

IPC分类号： B01D63/02

CPC分类号： B01D63/02 ,  B01D61/14 ,  B01D61/18 ,  B01D61/20 ,  B01D2311/20 ,  B01D2313/18 ,  B01D2313/24 ,  B01D2313/243 ,  B01D2315/06 ,  C02F1/444 ,  C02F2103/007 ,  C02F2103/42 ,  Y02W10/33 ,  Y02W10/37

摘要： Disclosed is an energy-saving and eco-friendly filtration system which is capable of minimizing the amount of the energy required for the filtration, thereby remarkably reducing the cost of water treatment. The filtration system of the present invention comprises: a feed water tank for storing a feed water to be treated; a hollow fiber membrane module for filtering the feed water supplied from the feed water tank; and a filtrate tank for storing a filtrate produced by the hollow fiber membrane module, wherein the hollow fiber membrane module comprises a plurality of hollow fiber membranes for filtering the feed water, and the sum of head pressure of the feed water in the feed water tank and water pressure of the filtrate in accordance with siphon principle is higher than the threshold membrane pressure of the hollow fiber membranes.

摘要翻译： 公开了一种节能环保的过滤系统，其能够最小化过滤所需的能量的量，从而显着降低了水处理的成本。 本发明的过滤系统包括：用于储存待处理给水的给水箱; 用于过滤从给水箱供给的给水的中空纤维膜组件; 以及用于储存由中空纤维膜组件制成的滤液的滤液槽，其中中空纤维膜组件包括用于过滤给水的多个中空纤维膜，以及给水箱中的给水的头部压力之和 滤液的水压根据虹吸原理高于中空纤维膜的膜膜压力。

公开(公告)号：US20140027360A1

公开(公告)日：2014-01-30

申请号：US14004769

申请日：2012-03-16

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： B01D63/02

CPC分类号： B01D63/02 ,  B01D61/18 ,  B01D63/04 ,  B01D65/00 ,  B01D2313/06 ,  B01D2313/12 ,  B01D2313/20 ,  B01D2315/06 ,  C02F1/44

摘要： Disclosed are a filtration apparatus having the advantages of conventional pressurized-type and submerged-type filtration apparatuses and a hollow fiber membrane module therefor. The filtration apparatus of the present invention comprises: a tank into which feed water is to be introduced, the tank comprising first and second inner step surfaces arranged opposite to each other; and a hollow fiber membrane module to be submerged in the feed water introduced in the tank, the hollow fiber membrane module comprising first and second headers and a hollow fiber membrane therebetween, wherein first and second ends of the first header are supported by the first and second inner step surfaces respectively.

摘要翻译： 公开了一种具有常规加压型和浸没式过滤装置及其中空纤维膜组件的优点的过滤装置。 本发明的过滤装置包括：供给水被引入的罐，所述罐包括彼此相对布置的第一和第二内台阶表面; 以及中空纤维膜组件，其浸没在引入到所述罐中的给水中，所述中空纤维膜组件包括第一和第二集管以及中间纤维膜，其中所述第一集管的第一和第二端由所述第一和第二集管支撑， 第二内部台阶表面。

公开(公告)号：US07534832B2

公开(公告)日：2009-05-19

申请号：US10505517

申请日：2002-12-26

申请人： Jeongheon Ahn ,  Seon-Hee Han ,  Kwang-Jin Lee

发明人： Jeongheon Ahn ,  Seon-Hee Han ,  Kwang-Jin Lee

IPC分类号： C08L53/00

CPC分类号： C08L55/02 ,  C08F257/02 ,  C08F265/04 ,  C08F265/06 ,  C08F265/08 ,  C08F285/00 ,  C08L27/06 ,  C08L51/003 ,  C08L51/04 ,  C08L67/02 ,  C08L69/00 ,  C08L2666/24 ,  C08L2666/02 ,  C08L2666/14 ,  C08L2666/04

摘要： The present invention relates to an acrylic impact modifier having a multilayered structure, which offers both superior impact resistance and coloring characteristics to engineering plastics, such as polycarbonate (PC) and a polycarbonate/polybutylene terephthalate alloy resin, or to a polyvinyl chloride resin. The present invention provides an acrylic impact modifier having a multilayered structure comprising: a) a seed prepared by emulsion copolymerization of a vinylic monomer and a hydrophilic monomer; b) a rubbery core surrounding the seed and comprising a C2 to C8 alkyl acrylate polymer, and c) a shell surrounding the rubbery core and comprising a C1, to C4 alkyl methacrylate polymer, a method for preparing the same, and a thermoplastic resin comprising the same.

摘要翻译： 本发明涉及一种具有多层结构的丙烯酸类抗冲击改性剂，其对工程塑料如聚碳酸酯（PC）和聚碳酸酯/聚对苯二甲酸丁二醇酯合成树脂或聚氯乙烯树脂具有优异的抗冲击性和着色特性。 本发明提供具有多层结构的丙烯酸类抗冲改性剂，其包含：a）通过乙烯基单体和亲水单体的乳液共聚制备的种子; b）包围种子并包含C 2至C 8烷基丙烯酸酯聚合物的橡胶芯，和c）包围橡胶芯并包含甲基丙烯酸C1-C4烷基酯聚合物的壳，其制备方法和包含 一样。

公开(公告)号：US06933758B2

公开(公告)日：2005-08-23

申请号：US10308453

申请日：2002-12-03

申请人： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

发明人： Tae-Hyoung Kim ,  Yong-Jin Yoon ,  Nam-Seog Kim ,  Kwang-Jin Lee

IPC分类号： G06F1/12 ,  G06F1/10 ,  H03K5/15 ,  H03L7/00 ,  H03L7/081 ,  H03L7/087

CPC分类号： H03L7/0814 ,  H03L7/087

摘要： A synchronous mirror delay circuit comprises a delay monitor circuit for delaying a reference clock signal from a clock buffer circuit. A forward delay array sequentially delays an output clock signal of the delay monitor circuit to generate delay clock signals, and the mirror control circuit detects a delay clock signal synchronized with the reference clock signal among the delay clock signals. A backward delay array delays a clock signal delayed by the mirror control circuit, and a clock driver receives an output clock signal of the backward delay array to generate the internal clock signal. A locking range control circuit controls a delay time of each clock signal transferred to the delay monitor circuit by the amount of a delay time of each signal transferred to the clock driver when none of delay clock signals of the forward delay array is synchronized with the reference clock signal.

摘要翻译： 同步镜延迟电路包括用于延迟来自时钟缓冲电路的参考时钟信号的延迟监视电路。 正向延迟阵列顺序地延迟延迟监视电路的输出时钟信号以产生延迟时钟信号，并且镜像控制电路在延迟时钟信号中检测与参考时钟信号同步的延迟时钟信号。 后向延迟阵列延迟由镜像控制电路延迟的时钟信号，并且时钟驱动器接收反向延迟阵列的输出时钟信号以产生内部时钟信号。 当前向延迟阵列的延迟时钟信号与参考信号同步时，锁定范围控制电路控制传送到延迟监视器电路的每个时钟信号的延迟时间达到传送到时钟驱动器的每个信号的延迟时间量 时钟信号。

公开(公告)号：US06735674B2

公开(公告)日：2004-05-11

申请号：US09886308

申请日：2001-06-21

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： G06F1200

CPC分类号： G06F12/0846 ,  G06F13/1631

摘要： A method and device for maintaining data coherency in a semiconductor memory device, having two or more memory chips combined into one chip and operated according to a late select synchronous pipeline type input/output protocol. A method includes the steps of generating first and second bypass summation signals by utilizing a chip block select address signal inputted in a latest write operation and comparison signals obtained from comparison between a latest write address and a current read address; and generating first and second bypass control signals having logic values contrary to each other by utilizing the first and second bypass summation signals and an internal clock signal, wherein a bypass operation is performed in one of read paths associated with the memory chips and a normal read operation is performed through other read paths when all the comparison signals are same.

摘要翻译： 一种用于在半导体存储器件中维持数据一致性的方法和装置，具有组合成一个芯片并根据后期选择同步流水线类型输入/输出协议进行操作的两个或多个存储器芯片。 一种方法包括以下步骤：通过利用在最新写入操作中输入的芯片块选择地址信号和从最新写入地址和当前读取地址之间的比较获得的比较信号来产生第一和第二旁路加和信号; 以及通过利用第一和第二旁路加法信号和内部时钟信号产生具有彼此相反的逻辑值的第一和第二旁路控制信号，其中在与存储器芯片相关联的读取路径和正常读取中执行旁路操作 当所有比较信号相同时，通过其它读取路径执行操作。

公开(公告)号：US06459637B1

公开(公告)日：2002-10-01

申请号：US09895196

申请日：2001-06-29

申请人： Kwang-Jin Lee ,  Jong-Cheol Lee

发明人： Kwang-Jin Lee ,  Jong-Cheol Lee

IPC分类号： G11C700

CPC分类号： G11C29/02 ,  G11C7/06 ,  G11C7/1045 ,  G11C2207/2254

摘要： An apparatus for controlling an enable of a sense amplifier in a semiconductor memory device includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.

摘要翻译： 一种用于控制半导体存储器件中的读出放大器的使能的装置包括用于重复地改变测试代码值的测试部件，直到读出放大器的使能相对于读出放大器要读取的数据为止为止，以及 用于在启用具有零余量的时间点确定测试代码值。 保险丝阵列切断与确定的测试代码值对应的保险丝。

公开(公告)号：US6166969A

公开(公告)日：2000-12-26

申请号：US345582

申请日：1999-06-30

申请人： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

发明人： Byoung-Cheol Song ,  Hak-Soo Yu ,  Kwang-Jin Lee

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/34 ,  H03K19/0185 ,  G11C7/00

CPC分类号： G11C7/06 ,  H03K19/018521

摘要： Disclosed is a level shifter that can receive and convert a first signal that can have various voltage logic levels to a second signal having internal voltage logic levels. The level shifter includes first and second ascending/descending circuits, where the first ascend/descending circuit receives the first signal and the second ascend/descending circuit receives an inverted first signal. Each ascend/descending circuit is operable to descend a high logic level of the received signal to a low output voltage level and ascend a low logic level of the received signal to a high output voltage level. The output voltages from the first and second ascending/descending circuits are input to a sense amplifier that amplifies the difference between the output voltages in order to generate the internal voltage logic levels of the second signal. The first and second ascending/descending circuits buffer their respective received signals using the high logic level of the input signal as a supply voltage. The same principles are also applicable to the level shifting from internal voltage logic levels to external voltage logic levels.

摘要翻译： 公开了一种电平转换器，其可以接收和转换可以具有各种电压逻辑电平的第一信号到具有内部电压逻辑电平的第二信号。 电平移位器包括第一和第二上升/下降电路，其中第一上升/下降电路接收第一信号，第二上升/下降电路接收反相的第一信号。 每个上升/下降电路可操作以将接收信号的高逻辑电平降低到低输出电压电平，并将接收信号的低逻辑电平上升到高输出电压电平。 来自第一和第二上升/下降电路的输出电压被输入到放大输出电压之间的差的读出放大器，以产生第二信号的内部电压逻辑电平。 第一和第二上升/下降电路使用输入信号的高逻辑电平作为电源电压来缓冲它们各自的接收信号。 相同的原理也适用于从内部电压逻辑电平转换到外部电压逻辑电平的电平。

公开(公告)号：US08980087B2

公开(公告)日：2015-03-17

申请号：US13141277

申请日：2009-12-22

申请人： Kwang-Jin Lee

发明人： Kwang-Jin Lee

IPC分类号： B01D61/18 ,  B01D61/22 ,  B01D61/20 ,  C02F1/44 ,  C02F1/00

CPC分类号： C02F1/44 ,  B01D61/18 ,  B01D61/20 ,  B01D61/22 ,  B01D65/02 ,  B01D2311/14 ,  B01D2315/06 ,  B01D2317/022 ,  B01D2317/04 ,  C02F2209/03 ,  C02F2303/20

摘要： A system and method for filtering is disclosed, which is capable of accomplishing a filtering operation at a high recovery rate of 96% or more, and realizing a compact and simplified system structure, the system comprising a water bath including an inlet and a discharging hole, wherein feed water to be treated is supplied to the inside of the water bath through the inlet, and concentrated water is discharged out through the discharging hole; and plural membrane cassettes including first and second membrane cassettes submerged into the feed water contained in the water bath, wherein the first membrane cassette is positioned nearest to the inlet, and the second membrane cassette is positioned nearest to the discharging hole, wherein the first membrane cassette treats the feed water with a first impurity concentration; the second membrane cassette treats the feed water with a second impurity concentration; and the first impurity concentration is smaller than the second impurity concentration.

摘要翻译： 公开了一种用于过滤的系统和方法，其能够以96％以上的高回收率实现过滤操作，并且实现了紧凑且简化的系统结构，该系统包括水浴，其包括入口和排出孔 其中待处理的给水通过入口供给到水浴的内部，并且浓缩的水通过排出孔排出; 以及多个膜盒，包括浸没在所述水浴中所含的给水中的第一和第二膜盒，其中所述第一膜盒位于最靠近所述入口的位置，所述第二膜盒位于最靠近所述排出孔的位置，其中所述第一膜 盒子以第一杂质浓度处理给水; 第二膜盒处理具有第二杂质浓度的给水; 并且第一杂质浓度小于第二杂质浓度。