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    Zero margin enable controlling apparatus and method of sense amplifier adapted to semiconductor memory device
    2.
    发明授权
    Zero margin enable controlling apparatus and method of sense amplifier adapted to semiconductor memory device 有权
    适用于半导体存储器件的读取放大器的零余量使能控制装置和方法

    公开(公告)号：US06459637B1

    公开(公告)日：2002-10-01

    申请号：US09895196

    申请日：2001-06-29

    申请人： Kwang-Jin Lee ,  Jong-Cheol Lee

    发明人： Kwang-Jin Lee ,  Jong-Cheol Lee

    IPC分类号： G11C700

    CPC分类号： G11C29/02 ,  G11C7/06 ,  G11C7/1045 ,  G11C2207/2254

    摘要： An apparatus for controlling an enable of a sense amplifier in a semiconductor memory device includes a test part for repeatedly varying a test code value until the enable of the sense amplifier has a zero margin with respect to data to be read by the sense amplifier, and for determining the test code value at a time point when the enable has the zero margin. A fuse array cuts a fuse corresponding to the determined test code value.

    摘要翻译： 一种用于控制半导体存储器件中的读出放大器的使能的装置包括用于重复地改变测试代码值的测试部件，直到读出放大器的使能相对于读出放大器要读取的数据为止为止，以及 用于在启用具有零余量的时间点确定测试代码值。 保险丝阵列切断与确定的测试代码值对应的保险丝。

    Semiconductor memory device with hierarchical bit line structure
    6.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US07489570B2

    公开(公告)日：2009-02-10

    申请号：US11480447

    申请日：2006-07-05

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C7/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。

    Method and circuit for writing double data rate (DDR) sampled data in a memory device
    8.
    发明申请
    Method and circuit for writing double data rate (DDR) sampled data in a memory device 失效
    用于在存储器件中写入双倍数据速率（DDR）采样数据的方法和电路

    公开(公告)号：US20050157827A1

    公开(公告)日：2005-07-21

    申请号：US11037602

    申请日：2005-01-18

    申请人： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

    发明人： Yong-Jin Yoon ,  Jong-Cheol Lee ,  Uk-Rae Cho

    IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/40 ,  H04L7/00

    CPC分类号： G11C7/1087 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1093

    摘要： A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first path control signal. Transferring third and fourth sampled input data to a second path using a second path control signal. The first and second path control signals are one half-cycle out of phase. First to fourth data are successively sampled in synchronization with a rising or falling edge of a first external clock signal; The sampled first data is linked onto a first path and the sampled second data is linked onto a second path in response to the first path control signal (generated in synchronization with a falling edge of the external clock signal); the first data on the first path and the second data on the second path are written to the memory cells in response to a write clock signal.

    摘要翻译： 一种用于在双倍数据速率（DDR）存储器件中采样和写入数据的方法和电路，能够确保足够的设置和保持余量而不考虑操作频率。 使用第一路径控制信号将第一和第二采样输入数据传送到第一路径。 使用第二路径控制信号将第三和第四采样输入数据传送到第二路径。 第一和第二路径控制信号是相位相差一个半周期。 与第一外部时钟信号的上升沿或下降沿同步地连续采样第一至第四数据; 响应于第一路径控制信号（与外部时钟信号的下降沿同步产生），采样的第一数据被链接到第一路径上，并且采样的第二数据被链接到第二路径上。 响应于写入时钟信号将第一路径上的第一数据和第二路径上的第二数据写入存储器单元。