公开(公告)号：US5982189A

公开(公告)日：1999-11-09

申请号：US856414

申请日：1997-05-14

申请人： Franco Motika ,  Phil Nigh ,  John Shushereba

发明人： Franco Motika ,  Phil Nigh ,  John Shushereba

IPC分类号： G01R31/30 ,  G01R27/26

CPC分类号： G01R31/30

摘要： A built-in stress circuit for an integrated circuit that has a frequency generator, at least one self-test circuit, a temperature regulator and a controller is disclosed. The frequency generator receives a reference clock and an adjusted temperature frequency from the temperature regulator and outputs the test frequencies needed for the self-test circuits. The self-test circuits, which are coupled to the frequency generator, receive the test frequencies and dissipate power as the self-test circuits are being used. The temperature regulator, which is coupled to the self-test circuits and the frequency generator, senses the power dissipated (i.e., the temperature), adjusts a temperature frequency corresponding to the temperature desired, and outputs the adjusted temperature frequency. The controller, which is coupled to the frequency generator, the self-test circuits, and the temperature regulator, provides the control data necessary for testing both electrical and thermal stress conditions.

摘要翻译： 公开了一种用于具有频率发生器，至少一个自检电路，温度调节器和控制器的集成电路的内置应力电路。 频率发生器从温度调节器接收参考时钟和调整的温度频率，并输出自检电路所需的测试频率。 耦合到频率发生器的自测电路在使用自检电路时接收测试频率并耗散功率。 耦合到自检电路和频率发生器的温度调节器感测功率消耗（即，温度），调节对应于期望温度的温度频率，并输出调节的温度频率。 耦合到频率发生器，自检电路和温度调节器的控制器提供测试电和热应力条件所需的控制数据。

公开(公告)号：US5973928A

公开(公告)日：1999-10-26

申请号：US135663

申请日：1998-08-18

申请人： Charles J. Blasi ,  Gobinda Das ,  Franco Motika

发明人： Charles J. Blasi ,  Gobinda Das ,  Franco Motika

IPC分类号： H01L23/12 ,  G01R1/067 ,  H01L23/50 ,  H01L23/64 ,  H01L25/00 ,  H01L25/16 ,  H05K1/02 ,  H05K7/02

CPC分类号： H05K1/0231 ,  H01L23/50 ,  H01L23/642 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/19105 ,  H01L2924/19106 ,  H05K2201/1053 ,  H05K2201/10704

摘要： A multi-layer ceramic module comprises a multi-layer ceramic substrate having an upper side and a lower side, at least one semiconductor chip mounted on the upper side of the substrate, a plurality of module pins projecting from the lower side of the substrate and at least one decoupling capacitor mounted on the lower side of the substrate between adjacent ones of the module pins.

摘要翻译： 多层陶瓷模块包括具有上侧和下侧的多层陶瓷基板，安装在基板的上侧的至少一个半导体芯片，从基板的下侧突出的多个模块销和 至少一个去耦电容器安装在相邻模块引脚之间的衬底的下侧。

公开(公告)号：US08769360B2

公开(公告)日：2014-07-01

申请号：US12904205

申请日：2010-10-14

申请人： Franco Motika ,  John D. Parker

发明人： Franco Motika ,  John D. Parker

IPC分类号： G06F11/00

CPC分类号： G06F11/2242 ,  G06F11/27

摘要： Exemplary embodiments include a sequential and concurrent status detection and evaluation method for multiple processor cores, including receiving data from a plurality of processor cores, for each of the plurality of processor cores, simultaneously running a built-in self test to determine if each of the plurality of cores has failed, checking the data for a dominant logic state and recording a subset of the plurality of processor cores that have failed.

摘要翻译： 示例性实施例包括用于多个处理器核的顺序和并发状态检测和评估方法，包括从多个处理器核心接收数据，用于多个处理器核心中的每一个，同时运行内置自我测试以确定每个处理器核心 多个核心已经失败，检查数据以获得主导逻辑状态并记录已经失败的多个处理器核心的子集。

公开(公告)号：US20140006889A1

公开(公告)日：2014-01-02

申请号：US13534444

申请日：2012-06-27

申请人： Franco Motika ,  Raymond J. Kurtulik ,  John D. Parker

发明人： Franco Motika ,  Raymond J. Kurtulik ,  John D. Parker

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/27 ,  G01R31/318547 ,  G01R31/3193

摘要： A method for detecting unstable signatures when testing a VLSI chip that includes adding to an LFSR one or more save and restore registers for storing an initial seed consisting of 0s and 1s; loading the initial seed into the one or more save and restoring LFSR registers upon reaching a predetermined number of test loops; performing a signature stability test by loading said initial seed to said LFSR, executing the predetermined number of BIST test loops, and comparing the resulting MISR signature for differences versus a previous signature stored in a MISR save and restore register.

摘要翻译： 一种用于在测试VLSI芯片时检测不稳定签名的方法，包括向LFSR添加一个或多个保存和恢复寄存器以存储由0和1组成的初始种子; 在达到预定数量的测试循环时将初始种子加载到一个或多个保存和恢复LFSR寄存器中; 通过将所述初始种子加载到所述LFSR来执行签名稳定性测试，执行预定数量的BIST测试循环，以及将差异的差异的MISR签名与存储在MISR保存和恢复寄存器中的先前签名进行比较。

公开(公告)号：US08087071B2

公开(公告)日：2011-12-27

申请号：US12329229

申请日：2008-12-05

申请人： Wayne Michael Delia ,  Edward Emile Kelley ,  Franco Motika

发明人： Wayne Michael Delia ,  Edward Emile Kelley ,  Franco Motika

IPC分类号： G06F17/30

CPC分类号： G06F21/32

摘要： An authentication method and system. A computing system generates an authentication table associated with a user. The computing system receives first authentication data and second authentication data differing from the first authentication data. The first authentication data and the second authentication data are placed in the authentication table. The authentication table comprising the first authentication data and the second authentication data is stored in the computing system. The computing system generates an action table. The computing system receives first action data and second action data and places the first action data and the second action data in the action table. The action table comprising the first action data and the second action data is stored in the computing system.

摘要翻译： 一种认证方法和系统。 计算系统生成与用户相关联的认证表。 计算系统接收与第一认证数据不同的第一认证数据和第二认证数据。 第一认证数据和第二认证数据被放置在认证表中。 包括第一认证数据和第二认证数据的认证表被存储在计算系统中。 计算系统生成一个动作表。 计算系统接收第一动作数据和第二动作数据，并将动作数据和第二动作数据放置在动作表中。 包括第一动作数据和第二动作数据的动作表被存储在计算系统中。

公开(公告)号：US07908534B2

公开(公告)日：2011-03-15

申请号：US12036320

申请日：2008-02-25

申请人： Franco Motika ,  Michael R. Ouellette ,  Phong T. Tran

发明人： Franco Motika ,  Michael R. Ouellette ,  Phong T. Tran

IPC分类号： G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/318536

摘要： A structural design-for-test for diagnosing broken scan chain defects of long non-scannable register chains (GPTR) The GPTR and the system for testing and diagnosing the broken LSSD scan-only chains rapidly localize defects to the failing Shift Register Latch (SRL) pair. The GPTR modifies the latches used in the GPTR scan chain to standard LSSD L1/L2 master-slave SRL type latch pairs; connects all the system ports of the L1 latches to the Shift Register Input (SRI) and clocked by the system C1-clk while the L1 scan port is clocked by the A-clk and L2 scan port is clocked only by the B-clk. The L1 latches are connected to at least one multiplexer having a first output connected to an input of each odd SRL, and a second output connected to an input port of each even SRL. In another embodiment, the GPTR includes a plurality of multiplexers respectively coupled to the master-slave latch pairs, wherein a first set of multiplexers have their respective output attached to an input of the odd L1 latches, and a second set of the multiplexers have their respective output attached to an input port of the even L1 latches.

摘要翻译： 用于诊断长不可扫描寄存器链（GPTR）的断层扫描链缺陷的结构设计 - 用于测试和诊断断裂的LSSD扫描链的系统快速将缺陷定位到故障移位寄存器锁存器（SRL） ）对。 GPTR将GPTR扫描链中使用的锁存器修改为标准LSSD L1 / L2主从SL型锁存器对; 将L1锁存器的所有系统端口连接到移位寄存器输入（SRI）并由系统C1-clk计时，而L1扫描端口由A-clk计时，L2扫描端口由B-clk提供时钟。 L1锁存器连接到至少一个多路复用器，其具有连接到每个奇数SRL的输入的第一输出，以及连接到每个偶数SRL的输入端口的第二输出。 在另一个实施例中，GPTR包括分别耦合到主从锁存器对的多个复用器，其中第一组复用器具有附加到奇数L1锁存器的输入的相应输出，并且第二组复用器具有它们 相应的输出附加到偶数L1锁存器的输入端口。

公开(公告)号：US20100115583A1

公开(公告)日：2010-05-06

申请号：US12263540

申请日：2008-11-03

申请人： Wayne Michael Delia ,  Edward Emile Kelley ,  Franco Motika

发明人： Wayne Michael Delia ,  Edward Emile Kelley ,  Franco Motika

IPC分类号： H04L9/32

CPC分类号： H04L9/3226 ,  H04L63/083

摘要： A method for user information authentication which includes setting user information for a user account, such user information being the set user information; inputting user information by a user for the user account into a device, such user information being the input user information; evaluating the input user information for correspondence with the set user information according to fault-tolerant user information rules, wherein such rules evaluate the input user information for content and closeness to the set user information and noting if the input user information is a valid user information, a fault-tolerant user information, or an invalid user information; authorizing access to the user account if the input user information is a valid user information. In one embodiment of the invention, the method includes incrementing an invalid user information counter only if the user information is an invalid user information. In another embodiment of the invention, the method includes providing a message to the user if the user information is a fault-tolerant user information, the message being descriptive of the input user information's correspondence with the fault tolerant user information rules.

摘要翻译： 一种用户信息认证方法，包括：设置用户账户的用户信息，所述用户信息为所述设置的用户信息; 用户将用户信息的用户信息输入到设备中，这样的用户信息是输入用户信息; 根据容错用户信息规则评估输入用户信息与设置的用户信息的对应关系，其中这样的规则评估用于内容的输入用户信息和与设置的用户信息的接近，并注意输入的用户信息是否是有效的用户信息 ，容错用户信息或无效用户信息; 如果输入的用户信息是有效的用户信息，则授权访问用户帐户。 在本发明的一个实施例中，该方法包括只有当用户信息是无效的用户信息时递增无效的用户信息计数器。 在本发明的另一个实施例中，该方法包括：如果用户信息是容错用户信息，则向用户提供消息，该消息描述输入用户信息与容错用户信息规则的对应关系。

公开(公告)号：US20090201131A1

公开(公告)日：2009-08-13

申请号：US12027540

申请日：2008-02-07

申请人： Wayne M. Delia ,  Edwards E. Kelley ,  Franco Motika

发明人： Wayne M. Delia ,  Edwards E. Kelley ,  Franco Motika

IPC分类号： H04Q5/22

CPC分类号： G07D7/01

摘要： A system and method of determining likelihood of counterfeiting without inspection of currency compares signals returned by uniquely customized RFID chips when interrogated, preferably incident to a transaction. The RFID information is compared to RFID information for bills known to be in circulation in order to validate a given currency bill. Usage patterns can be determined from statistical analysis of such reports and reported usage patterns will statistically differ significantly if not radically with the number of RFID chips returning the same RFID information and such differences will increase in either or both of geographic locations of reports and frequency of reports with increase of the number of bills having duplicated RFID chips. The basic infrastructure for practice of the invention is also capable of tracking genuine currency following, for example, a theft or other criminal activity.

摘要翻译： 在不检查货币的情况下确定伪造可能性的系统和方法比较了由特制定制的RFID芯片在询问时返回的信号，优选事件事件发生在交易中。 将RFID信息与已知流通的票据的RFID信息进行比较，以验证给定的货币票据。 使用模式可以从这样的报告的统计分析中确定，如果RFID芯片返回相同的RFID信息的数量不是很大，报告的使用模式将有统计上的显着差异，并且这些差异将在报告的地理位置和频率的两个或两个之间增加 报告说，具有复制的RFID芯片的钞票数量增加。 本发明实践的基本基础也能跟踪真实的货币，例如盗窃或其他犯罪活动。

公开(公告)号：US20080211531A1

公开(公告)日：2008-09-04

申请号：US12119834

申请日：2008-05-13

申请人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

发明人： Anne E. Gattiker ,  David A. Grosch ,  Marc D. Knox ,  Franco Motika ,  Phil Nigh ,  Jody Van Horn ,  Paul S. Zuchowski

IPC分类号： G01R31/26

CPC分类号： G01R31/2879 ,  G01R31/275 ,  G01R31/3008 ,  G01R31/31858

摘要： Methods for testing a semiconductor circuit (10) including testing the circuit and modifying a well bias (14, 18) of the circuit during testing. The methods improve the resolution of voltage-based and IDDQ testing and diagnosis by modifying well bias during testing. In addition, the methods provide more efficient stresses during stress testing. The methods apply to ICs where the semiconductor well (wells and/or substrates) are wired separately from the chip VDD and GND, allowing for external control (40) of the well potentials during test. In general, the methods rely on using the well bias to change transistor threshold voltages.

公开(公告)号：US20070162240A1

公开(公告)日：2007-07-12

申请号：US11327818

申请日：2006-01-06

申请人： Samuel Foster ,  Franco Motika

发明人： Samuel Foster ,  Franco Motika

IPC分类号： G01R29/26

CPC分类号： G01R31/31709

摘要： A system and a method for measuring and quantitatively analyzing the jitter in repetitive electrical signals in a chip using a tester are described. The tester sorts chips based on the jitter measurements, thereby eliminating the need for external instrumentation. The waveform is sampled by the tester at various points of a period over a large number of periods and results are collected. The data is analyzed to determine the total range where the waveform is found to undergo a transition. The transition area is further analyzed to pinpoint the precise location of the transition for each period of the repetitive waveform. The data is used to quantify the jitter by means of statistical analyses, the results of which are used by the tester to sort the chips by comparing the calculated jitter characteristics to predetermined criteria.