公开(公告)号：US4271408A

公开(公告)日：1981-06-02

申请号：US84384

申请日：1979-10-12

申请人： Toru Teshima ,  Jun-ichi Nishizawa ,  Yasunori Kishi

发明人： Toru Teshima ,  Jun-ichi Nishizawa ,  Yasunori Kishi

IPC分类号： G08G1/095 ,  G09F13/04 ,  G09F13/22 ,  G08B5/36

CPC分类号： G09F13/22 ,  G08G1/095 ,  G09F2013/0472 ,  G09F2013/222 ,  Y10S362/80 ,  Y10S362/812

摘要： A plurality of cellular concave mirror surfaces are formed on a plate-like reflector unit, and a plurality of light-emitting diodes are disposed on these cellular concave mirror surfaces to jointly form a colored light source. Connection wirings to be connected with a power supply source are provided on a substrate laminated with the reflector unit. A lamp base of a conventional type may be coupled to the substrate for being electrically connected to the wirings. This colored light source can provide a single or multiple color displays. Improved shadow pattern display can be provided by forming a complementary color pattern on a front cover lens. Letter, symbol or pattern display can be provided by selectively arranging light-emitting diodes on the reflector unit. In case the above-mentioned light source is used as a traffic signal device, power dissipation and maintenance care are reduced by the light-emitting diodes having low power consumption and long service life, and high security of the traffic is assured by the elimination of false indications caused by external lights.

摘要翻译： 在板状反射器单元上形成多个细胞凹面镜面，并且在这些细胞凹面镜面上配置多个发光二极管，共同形成着色光源。 在与反射器单元层叠的基板上设置与电源连接的连接配线。 常规类型的灯座可以耦合到基板，用于电连接到布线。 这种彩色光源可以提供单个或多个彩色显示器。 可以通过在前盖透镜上形成补色图案来提供改进的阴影图案显示。 可以通过在反射器单元上选择性地布置发光二极管来提供字母，符号或图案显示。 在将上述光源用作交通信号装置的情况下，通过具有低功耗和长使用寿命的发光二极管来降低功耗和维护保养，并且通过消除交通信号来保证高安全性 外部灯光引起的虚假指示。

公开(公告)号：US4171995A

公开(公告)日：1979-10-23

申请号：US760370

申请日：1977-01-18

申请人： Jun-ichi Nishizawa ,  Kentaro Nakamura ,  Takashi Kitsuregawa

发明人： Jun-ichi Nishizawa ,  Kentaro Nakamura ,  Takashi Kitsuregawa

IPC分类号： H01L21/329 ,  H01L29/739 ,  H01L21/20 ,  H01L21/22

CPC分类号： H01L29/66356 ,  H01L29/7392 ,  Y10S148/088

摘要： A process of manufacturing a static induction thyristor comprising providing a semiconductor substrate of the first conductivity type which defines a first semiconductor layer and forming a second semiconductor layer thereon of a second conductivity type. The first and second semiconductor layers have relative impurity concentrations effective for forming therebetween charge depletion regions when no electrical signal is applied to the second semiconductor layer and which prevent injection of charge carriers through the second semiconductor layer when the thyristor is in a blocking state, and such that electrically forward biasing the second semiconductor layer effectuates a sufficient reduction of the depletion regions that a sufficient quantity of charge carriers may be injected through the second semiconductor layer that the thryistor switches to a conductive state. The second semiconductor layer defines the gate region of the thyristor.

摘要翻译： 一种制造静态感应晶闸管的方法，包括提供限定第一半导体层并在其上形成第二导电类型的第二半导体层的第一导电类型的半导体衬底。 当第二半导体层没有电信号施加到第二半导体层上时，第一和第二半导体层具有有效的用于在其间形成电荷耗尽区的相对杂质浓度，并且当晶闸管处于阻塞状态时，阻止注入电荷载流子穿过第二半导体层， 使得向前偏置第二半导体层的方式实现耗尽区域的足够的减少，使得能够通过第二半导体层注入足够量的电荷载流子，使得晶闸管切换到导通状态。 第二半导体层限定晶闸管的栅极区域。

公开(公告)号：US4160259A

公开(公告)日：1979-07-03

申请号：US757583

申请日：1976-12-27

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/772 ,  H01L29/78 ,  H01L29/808 ,  H01L29/812 ,  H01L29/76

CPC分类号： H01L29/7722 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/7831 ,  H01L29/7832 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/8124 ,  H01L2924/10158

摘要： In a transistor structure having a pair of current electrodes and a control electrode, at least one control electrode is added to vary the negative feed-back resistance in the current path. In a typical example, both the triode-like and the pentode-like characteristics are provided by the control in the voltage applied to the additional control electrode for varying the negative feed-back resistance r.sub.s, thereby changing the product G.sub.m .multidot.r.sub.s from less than unity to greater than unity where G.sub.m is the transconductance.

公开(公告)号：US4086611A

公开(公告)日：1978-04-25

申请号：US733930

申请日：1976-10-19

申请人： Jun-ichi Nishizawa ,  Kentaro Nakamura ,  Takashi Kitsuregawa

发明人： Jun-ichi Nishizawa ,  Kentaro Nakamura ,  Takashi Kitsuregawa

IPC分类号： H01L29/739 ,  H01L29/74

CPC分类号： H01L29/7392 ,  Y10S148/088

摘要： The disclosed thyristor comprises an n.sup.- semi-conductor layer, a p.sup.- semiconductor layer disposed on one surface of the n.sup.- layer to form a pn junction between them, an n.sup.+ and a p.sup.+ semiconductor layer disposed on the other surfaces of the n.sup.- and p.sup.- layers respectively to serve as main electrodes and a p.sup.+ and a n.sup.+ apertured gate layers disposed within the n.sup.- and p.sup.- layers respectively and provided with a gate electrode. An intrinsic semiconductor layer may be substituted for the n.sup.- and p.sup.- layers. A process of producing such a thyristor is also disclosed.

摘要翻译： 公开的晶闸管包括n型半导体层，p-半导体层，其设置在n层的一个表面上以在它们之间形成pn结，n +和p +半导体层设置在n- 和p层分别用作主电极和分别设置在n层和p层内的p +和n +孔栅层，并设置有栅电极。 本征半导体层可以代替n层和p层。 还公开了制造这种晶闸管的工艺。

公开(公告)号：US5532511A

公开(公告)日：1996-07-02

申请号：US409684

申请日：1995-03-23

申请人： Jun-ichi Nishizawa ,  Toru Kurabayashi

发明人： Jun-ichi Nishizawa ,  Toru Kurabayashi

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L29/772 ,  H01L29/80 ,  H01L29/04 ,  H01L31/036 ,  H01L31/112

CPC分类号： H01L29/66454 ,  H01L21/28587 ,  H01L29/7722 ,  H01L29/802

摘要： A semiconductor device includes a substrate crystal of a type for epitaxial growth thereon. The substrate crystal has a (111)A face and a (111)B face. Also provided are at least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition, thereby providing a structure having a source and a drain. A gate side includes the (111)B face of the substrate crystal. A gate insulating layer is deposited by way of epitaxial growth on the gate side according to molecular layer epitaxy. Alternatively, the at least two semiconductor regions may be deposited on the (111)B face of the substrate crystal according to molecular layer epitaxy, and the gate insulating layer may be deposited on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition.

摘要翻译： 半导体器件包括其上用于外延生长的类型的衬底晶体。 衬底晶体具有（111）A面和（111）B面。 还提供了根据金属有机化学气相沉积在衬底晶体的（111）A面上通过外延生长沉积的不同导电类型的至少两个半导体区域，由此提供具有源极和漏极的结构。 栅极侧包括衬底晶体的（111）B面。 根据分子层外延，栅极绝缘层通过外延生长沉积在栅极侧。 或者，可以根据分子层外延将至少两个半导体区域沉积在衬底晶体的（111）B面上，并且栅极绝缘层可以根据金属沉积在衬底晶体的（111）A面上 有机化学气相沉积。

公开(公告)号：US5500079A

公开(公告)日：1996-03-19

申请号：US237417

申请日：1994-05-03

申请人： Jun-ichi Nishizawa ,  Kenji Yamamoto

发明人： Jun-ichi Nishizawa ,  Kenji Yamamoto

IPC分类号： H01L21/302 ,  H01L21/203 ,  H01L21/268 ,  H01L21/306 ,  H01L21/00

CPC分类号： H01L21/30621 ,  H01L21/2686

摘要： A semiconductor material to be etched is held in a reaction chamber at a predetermined temperature. A reactive etching gas such as a chlorine gas is introduced into the reaction chamber for a first period of time. Thereafter, the reaction chamber is evacuated for a second period of time, and ultraviolet radiation is applied to the semiconductor material for a third period of time within the second period of time for thereby etching the semiconductor material to a depth on the order of a molecular or atomic layer.

摘要翻译： 将要蚀刻的半导体材料在预定温度下保持在反应室中。 反应性蚀刻气体如氯气在反应室中被引入第一段时间。 此后，将反应室抽真空第二时间，并且在第二时间段内对半导体材料施加紫外线辐射第三时间，从而将半导体材料蚀刻到分子量级的深度 或原子层。

公开(公告)号：US5485017A

公开(公告)日：1996-01-16

申请号：US241447

申请日：1994-05-11

申请人： Jun-ichi Nishizawa

发明人： Jun-ichi Nishizawa

IPC分类号： H01L21/329 ,  H01L29/739 ,  H01L29/861 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/66356 ,  H01L29/66196 ,  H01L29/739 ,  H01L29/8616

摘要： A semiconductor device has an n.sup.+ source region, a first n.sup.- channel region, a barrier layer, a second n.sup.- channel region, a pair of n.sup.+ drain regions, an insulating film, and a pair of metal electrodes over the respective n.sup.+ drain regions, all successively disposed on an upper surface of an n.sup.+ crystal substrate. The drain regions and the metal electrodes jointly provide a storage electric capacitance. A source electrode is disposed on the lower surface of the n.sup.+ crystal substrate. Bit information can be written and read at a high speed by tunneling through the barrier layer. According to a method of manufacturing the above semiconductor device, the n.sup.+ source region, the first n.sup.- channel region, the barrier layer, the second n.sup.- channel region, the n.sup.+ drain regions, the insulating film, and the metal electrodes are successively deposited on the n.sup.+ crystal substrate in a growing apparatus. The metal electrodes and the source electrode are formed by depositing a metal and a low-resistance semiconductor selectively or both in one location within the growing apparatus.

摘要翻译： 半导体器件在各个n +漏极区域上具有n +源极区，第一n沟道区，势垒层，第二n沟道区，一对n +漏极区，绝缘膜和一对金属电极 ，全部依次设置在n +晶体基板的上表面上。 漏极区域和金属电极共同提供存储电容。 源电极设置在n +晶体基板的下表面上。 通过穿过阻挡层可以高速写入和读取位信息。 根据制造上述半导体器件的方法，依次沉积n +源极区，第一n-沟道区，势垒层，第二n-沟道区，n +漏极区，绝缘膜和金属电极 在生长装置中的n +晶体衬底上。 金属电极和源电极通过在生长装置内的一个位置中选择性地或两者沉积金属和低电阻半导体而形成。

公开(公告)号：US5475242A

公开(公告)日：1995-12-12

申请号：US425250

申请日：1995-04-17

申请人： Jun-ichi Nishizawa ,  Nobuo Takeda ,  Toshiyuki Kishine

发明人： Jun-ichi Nishizawa ,  Nobuo Takeda ,  Toshiyuki Kishine

IPC分类号： H01L27/092 ,  H01L29/78 ,  H01L21/33

CPC分类号： H01L27/092

摘要： A notched insulation gate static induction transistor integrated circuit ording to the present invention comprises an enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to prevent current from flowing in a standby mode, and a depletion enhancement mode CMOS logic circuit including a notched insulation gate static induction transistor in which a threshold voltage is determined to cause current to slightly flow in the standby mode. The enhancement mode CMOS logic circuit and the depletion enhancement mode CMOS logic circuit are formed on a major surface of a substrate, and the depletion enhancement mode CMOS logic circuit is used in a circuit in which an average power consumption in a switching operation is higher than that in the standby mode.

摘要翻译： 根据本发明的缺口绝缘栅静电感应晶体管集成电路包括增强模式CMOS逻辑电路，其包括其中确定阈值电压以防止电流在待机模式下流动的缺口绝缘栅静电感应晶体管，以及耗尽增强 模式CMOS逻辑电路，其包括在待机模式下确定阈值电压以使电流稍微流动的缺口绝缘栅静电感应晶体管。 增强模式CMOS逻辑电路和耗尽增强模式CMOS逻辑电路形成在衬底的主表面上，并且耗尽增强模式CMOS逻辑电路用于其中开关操作中的平均功耗高于 在待机模式下。

公开(公告)号：US5254207A

公开(公告)日：1993-10-19

申请号：US983331

申请日：1992-11-30

申请人： Jun-ichi Nishizawa ,  Toru Kurabayashi

发明人： Jun-ichi Nishizawa ,  Toru Kurabayashi

IPC分类号： C30B25/02 ,  C30B23/02 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16 ,  H01L21/205

CPC分类号： C30B25/105 ,  C30B23/002 ,  C30B23/02 ,  C30B29/42

摘要： Material and impurity gases are introduced into a crystal growth chamber to grow a crystal film on a GaAs substrate. A light beam emitted from a variable-wavelength light source is applied to the crystal film being grown on the substrate while varying the wavelength of the light beam. The dependency, on the wavelength of the light beam, of the intensity of light reflected by the crystal film is measured, and an optimum wavelength is selected for measurement depending on the type of molecules adsorbed while the crystal film is being grown. Light is then applied at the optimum wavelength to the crystal film being grown, and a time-dependent change in the intensity of light reflected by the crystal film is measured. The rate at which the material gases are introduced into the crystal growth chamber is adjusted to control the growth rate of the crystal film, the composition ratio of a mixed crystal thereof, and the density of the impurity therein.

公开(公告)号：US5027180A

公开(公告)日：1991-06-25

申请号：US423661

申请日：1989-10-18

申请人： Jun-ichi Nishizawa ,  Hisao Kondoh

发明人： Jun-ichi Nishizawa ,  Hisao Kondoh

IPC分类号： H01L29/74 ,  H01L29/10 ,  H01L29/739

CPC分类号： H01L29/1066 ,  H01L29/7392

摘要： A double gate static induction thyristor comprises a semiconductor substrate, a first gate region formed at a first principal surface of the substrate, and a first semiconductor region of a first conduction type formed on the same first principal surface. A second gate region is formed at a second principal surface of the substrate, and a second semiconductor region of a second conduction type is formed on the same second principal surface. Gate electrodes are formed on the first and second gate regions, and main electrodes are formed on the first and second semiconductor regions, so that portions of the semiconductor regions surrounded by the gate regions form a current path between the main electrodes. Further, impurity is deeply diffused in portions of the first and second gate regions formed with the gate electrodes.

摘要翻译： 双栅极静电感应晶闸管包括半导体衬底，形成在衬底的第一主表面处的第一栅极区域和形成在相同的第一主表面上的第一导电类型的第一半导体区域。 第二栅极区域形成在基板的第二主表面处，并且第二导电类型的第二半导体区域形成在相同的第二主表面上。 栅电极形成在第一和第二栅极区上，并且主电极形成在第一和第二半导体区上，使得被栅极区包围的半导体区域的部分在主电极之间形成电流路径。 此外，在形成有栅电极的第一和第二栅极区域的部分中，杂质被深度扩散。