公开(公告)号：US20120025282A1

公开(公告)日：2012-02-02

申请号：US12848494

申请日：2010-08-02

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/94 ,  H01L27/088 ,  H01L21/336 ,  H01L27/105

CPC分类号： H01L27/1203 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/84 ,  H01L29/66628

摘要： In one exemplary embodiment of the invention, a semiconductor structure includes: a substrate; and a plurality of devices at least partially overlying the substrate, where the plurality of devices include a first device coupled to a second device via a first raised source/drain having a first length, where the first device is further coupled to a second raised source/drain having a second length, where the first device comprises a transistor, where the first raised source/drain and the second raised source/drain at least partially overly the substrate, where the second raised source/drain comprises a terminal electrical contact, where the second length is greater than the first length.

公开(公告)号：US08084309B2

公开(公告)日：2011-12-27

申请号：US12542179

申请日：2009-08-17

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： A method of fabricating an electronic structure is provided that includes forming a first conductivity doped first semiconductor material on the SOI semiconductor layer of a substrate. The SOI semiconductor layer has a thickness of less than 10 nm. The first conductivity in-situ doped first semiconductor material is removed from a first portion of the SOI semiconductor layer, wherein a remaining portion of the first conductivity in-situ doped first semiconductor material is present on a second portion of SOI semiconductor layer. A second conductivity in-situ doped second semiconductor material is formed on the first portion of the SOI semiconductor layer, wherein a mask prohibits the second conductivity in-situ doped semiconductor material from being formed on the second portion of the SOI semiconductor layer. The dopants from the first and second conductivity in-situ doped semiconductor materials are diffused into the first semiconductor layer to form dopant regions.

摘要翻译： 提供一种制造电子结构的方法，其包括在衬底的SOI半导体层上形成第一导电掺杂的第一半导体材料。 SOI半导体层的厚度小于10nm。 第一导电性原位掺杂的第一半导体材料从SOI半导体层的第一部分去除，其中第一导电性原位掺杂的第一半导体材料的剩余部分存在于SOI半导体层的第二部分上。 第二导电性原位掺杂的第二半导体材料形成在SOI半导体层的第一部分上，其中掩模禁止在SOI半导体层的第二部分上形成第二导电性原位掺杂半导体材料。 来自第一和第二导电性原位掺杂半导体材料的掺杂剂扩散到第一半导体层中以形成掺杂区域。

公开(公告)号：US20110309446A1

公开(公告)日：2011-12-22

申请号：US12816399

申请日：2010-06-16

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/12 ,  H01L21/8238 ,  H01L29/786 ,  H01L21/336

CPC分类号： H01L29/66477 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618

摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.

摘要翻译： 一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一 在图案化的栅极结构下方的半导体衬底的沟道区上。

公开(公告)号：US20110254080A1

公开(公告)日：2011-10-20

申请号：US12760287

申请日：2010-04-14

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Wilfried E. Haensch ,  Ali Khakifirooz ,  Isaac Lauer ,  Ghavam G. Shahidi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/78

摘要： A method for fabricating an FET device characterized as being a tunnel FET (TFET) device is disclosed. The method includes processing a gate-stack, and processing the adjoining source and drain junctions, which are of a first conductivity type. A hardmask is formed covering the gate-stack and the junctions. A tilted angle ion implantation is performed which is received by a first portion of the hardmask, and it is not received by a second portion of the hardmask due to the shadowing of the gate-stack. The implanted portion of the hardmask is removed and one of the junctions is exposed. The junction is etched away, and a new junction, typically in-situ doped to a second conductivity type, is epitaxially grown into its place. A device characterized as being an asymmetrical TFET is also disclosed. The source and drain junctions of the TFET are of different conductivity types, and the TFET also includes spacer formations in a manner that the spacer formation on one side of the gate-stack is thinner than on the other side of the gate-stack.

摘要翻译： 公开了一种用于制造FET器件的方法，其特征在于是隧道FET（TFET）器件。 该方法包括处理栅极堆叠，以及处理第一导电类型的邻接的源极和漏极结。 形成覆盖栅极堆叠和结的硬掩模。 执行由硬掩模的第一部分接收的倾斜角度离子注入，并且由于栅极堆叠的阴影而不被硬掩模的第二部分接收。 去除硬掩模的注入部分，并露出其中一个接头。 该结被蚀刻掉，并且通常原位掺杂到第二导电类型的新结，外延生长到其位置。 还公开了一种特征为不对称TFET的器件。 TFET的源极和漏极结具有不同的导电类型，并且TFET还包括间隔物结构，使得栅极堆叠的一侧上的间隔物形成比栅极堆叠的另一侧更薄。

公开(公告)号：US20110227165A1

公开(公告)日：2011-09-22

申请号：US13151525

申请日：2011-06-02

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L27/092

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

公开(公告)号：US08022488B2

公开(公告)日：2011-09-20

申请号：US12566004

申请日：2009-09-24

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

摘要： A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

摘要翻译： 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底的上表面上的至少一个栅堆叠，例如FET。 该结构还包括在至少一个栅极堆叠的沟道上引起应变的第一外延半导体材料。 第一外延半导体材料位于至少一个栅极堆叠的基准面上，基本上位于衬底中的存在于至少一个栅极堆叠的相对侧上的一对凹陷区域内。 扩散扩展区域位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散扩展区的上表面上的第二外延半导体材料。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

公开(公告)号：US07993999B2

公开(公告)日：2011-08-09

申请号：US12614906

申请日：2009-11-09

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Johnathan E. Faltermeier ,  Ali Khakifirooz

IPC分类号： H01L21/8238

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/66795

摘要： A device and method for fabrication of fin devices for an integrated circuit includes forming fin structures in a semiconductor material of a semiconductor device wherein the semiconductor material is exposed on sidewalls of the fin structures. A donor material is epitaxially deposited on the exposed sidewalls of the fin structures. A condensation process is applied to move the donor material through the sidewalls into the semiconductor material such that accommodation of the donor material causes a strain in the semiconductor material of the fin structures. The donor material is removed, and a field effect transistor is formed from the fin structure.

摘要翻译： 用于制造用于集成电路的鳍片器件的器件和方法包括在半导体器件的半导体材料中形成鳍结构，其中半导体材料暴露在鳍结构的侧壁上。 施主材料外延地沉积在鳍结构的暴露的侧壁上。 施加冷凝过程以将供体材料通过侧壁移动到半导体材料中，使得供体材料的调节在翅片结构的半导体材料中引起应变。 施主材料被去除，并且从翅片结构形成场效应晶体管。

公开(公告)号：US20110115023A1

公开(公告)日：2011-05-19

申请号：US12621460

申请日：2009-11-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ghavam G. Shahidi

IPC分类号： H01L27/088 ,  H01L21/8238

CPC分类号： H01L21/845 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/785

摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.

摘要翻译： 公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。 沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。 三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。 三种不同类型的设备中的每一种具有单独优化的阈值。 还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。 该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

公开(公告)号：US20110042728A1

公开(公告)日：2011-02-24

申请号：US12542748

申请日：2009-08-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Charles William Koburger, III

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Charles William Koburger, III

IPC分类号： H01L29/78 ,  H01L21/31 ,  H01L21/318 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/8238

CPC分类号： H01L21/3185 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/76834 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7845

摘要： In one embodiment, a method is provided for forming stress in a semiconductor device. The semiconductor device may include a gate structure on a substrate, wherein the gate structure includes at least one dummy material that is present on a gate conductor. A conformal dielectric layer is formed atop the semiconductor device, and an interlevel dielectric layer is formed on the conformal dielectric layer. The interlevel dielectric layer may be planarized to expose at least a portion of the conformal dielectric layer that is atop the gate structure, in which the exposed portion of the conformal dielectric layer may be removed to expose an upper surface of the gate structure. The upper surface of the gate structure may be removed to expose the gate conductor. A stress inducing material may then be formed atop the at least one gate conductor.

摘要翻译： 在一个实施例中，提供了一种用于在半导体器件中形成应力的方法。 半导体器件可以在衬底上包括栅极结构，其中栅极结构包括存在于栅极导体上的至少一个虚拟材料。 在半导体器件顶部形成保形电介质层，并且在保形电介质层上形成层间电介质层。 层间电介质层可以被平坦化以暴露在栅极结构顶部的保形电介质层的至少一部分，其中共形介电层的暴露部分可被去除以暴露栅极结构的上表面。 可以去除栅极结构的上表面以露出栅极导体。 然后可以在至少一个栅极导体上方形成应力诱导材料。

公开(公告)号：US20100203732A1

公开(公告)日：2010-08-12

申请号：US12368561

申请日：2009-02-10

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/302 ,  H01L21/30 ,  H01L21/308

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

摘要翻译： 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。