公开(公告)号：US20100203732A1

公开(公告)日：2010-08-12

申请号：US12368561

申请日：2009-02-10

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/302 ,  H01L21/30 ,  H01L21/308

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

摘要翻译： 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。

公开(公告)号：US08222154B2

公开(公告)日：2012-07-17

申请号：US12368561

申请日：2009-02-10

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Geng Wang

IPC分类号： H01L21/302

CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/26586 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32134 ,  H01L21/32135 ,  H01L29/66795 ,  Y10S438/942 ,  Y10S438/947

摘要： A semiconductor device is formed by providing a substrate and forming a semiconductor-containing layer atop the substrate. A mask having a plurality of openings is then formed atop the semiconductor-containing layer, wherein adjacent openings of the plurality of openings of the mask are separated by a minimum feature dimension. Thereafter, an angled ion implantation is performed to introduce dopants to a first portion of the semiconductor-containing layer, wherein a remaining portion that is substantially free of dopants is present beneath the mask. The first portion of the semiconductor-containing layer containing the dopants is removed selective to the remaining portion of semiconductor-containing layer that is substantially free of the dopants to provide a pattern of sublithographic dimension, and the pattern is transferred into the substrate to provide a fin structure of sublithographic dimension.

摘要翻译： 通过提供衬底并在衬底上形成含半导体的层来形成半导体器件。 然后在半导体含有层顶上形成具有多个开口的掩模，其中掩模的多个开口中的相邻开口被最小特征尺寸分开。 此后，进行成角度的离子注入以将掺杂剂引入到半导体含有层的第一部分，其中基本上不含掺杂剂的剩余部分存在于掩模下方。 含有掺杂剂的含半导体层的第一部分被选择性地除去基本上不含掺杂剂的半导体含有层的剩余部分，以提供亚光刻尺寸的图案，并且将图案转移到衬底中以提供 翅片结构的亚光刻尺寸。

公开(公告)号：US09054211B2

公开(公告)日：2015-06-09

申请号：US13540801

申请日：2012-07-03

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

公开(公告)号：US08994085B2

公开(公告)日：2015-03-31

申请号：US13551714

申请日：2012-07-18

申请人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC分类号： H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

摘要翻译： 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

公开(公告)号：US08710588B2

公开(公告)日：2014-04-29

申请号：US13595025

申请日：2012-08-27

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Dechao Guo ,  Pranita Kulkarni ,  Philip J. Oldiges ,  Ghavam G. Shahidi

IPC分类号： H01L27/12

CPC分类号： H01L29/66636 ,  H01L29/66772 ,  H01L29/78621 ,  H01L29/78654

摘要： A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

摘要翻译： 公开了半导体器件和制造半导体器件的方法。 在一个实施例中，该方法包括提供半导体衬底，在衬底上外延生长Ge层，并在Ge层上外延生长半导体层，其中半导体层的厚度为10nm或更小。 该方法还包括去除Ge层的至少一部分以在Si层下形成空隙，并且至少部分地用电介质材料填充空隙。 以这种方式，半导体层成为非常薄的绝缘体上半导体层。 在一个实施例中，在空隙填充有电介质材料之后，在半导体层上生长原位掺杂的源极和漏极区。 在一个实施例中，该方法还包括退火所述源区和漏区以在半导体层中形成掺杂的延伸区。

公开(公告)号：US08653596B2

公开(公告)日：2014-02-18

申请号：US13344885

申请日：2012-01-06

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L21/70 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC分类号： H01L29/945 ,  H01L21/84 ,  H01L27/1052 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1116 ,  H01L27/1203 ,  H01L27/1207

摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.

摘要翻译： 集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。 可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。 在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。 还公开了制造集成电路的方法。

公开(公告)号：US20140024215A1

公开(公告)日：2014-01-23

申请号：US13555306

申请日：2012-07-23

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

IPC分类号： B44C1/22 ,  H01B13/00 ,  H01L21/308

CPC分类号： H01L21/3086 ,  H01B13/00 ,  H01B19/04 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/32134 ,  H01L21/32137

摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

摘要翻译： 公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。 该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。 具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。 然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。 一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。 取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

公开(公告)号：US20140024191A1

公开(公告)日：2014-01-23

申请号：US13555240

申请日：2012-07-23

申请人： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

发明人： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

IPC分类号： H01L21/31 ,  H01L21/336

CPC分类号： H01L21/0274 ,  H01L21/26586 ,  H01L21/3081 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.

摘要翻译： 使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。 该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

公开(公告)号：US08629504B2

公开(公告)日：2014-01-14

申请号：US13433401

申请日：2012-03-29

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ghavam G. Shahidi

IPC分类号： H01L21/00

CPC分类号： H01L27/1214 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/13

摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.

摘要翻译： 提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。 在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。 由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。 还提供了形成上述电气装置的方法。

公开(公告)号：US20140001555A1

公开(公告)日：2014-01-02

申请号：US13537141

申请日：2012-06-29

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。