公开(公告)号：US06891770B2

公开(公告)日：2005-05-10

申请号：US10920421

申请日：2004-08-18

申请人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Takafumi Takatsuka ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C11/403 ,  G11C8/18 ,  G11C11/406 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C8/18 ,  G11C11/406 ,  G11C11/408

摘要： Activation/inactivation of an internal normal row activation signal for controlling a memory cell selecting operation is controlled in response to leading and trailing edges of an address transition detection signal. When an internal normal row activating signal is activated, generation of an address transition detection signal is masked by mask circuitry. Conflict between an activating operation and an inactivating operation of the normal row activating signal can be prevented and an internal operation can be performed stably. A refresh-control-free dynamic semiconductor memory device having an interface compatible with a static random access memory and capable of stably performing an internal operation is provided.

摘要翻译： 响应于地址转换检测信号的前沿和后沿来控制用于控制存储器单元选择操作的内部正常行激活信号的激活/去激活。 当内部正常行激活信号被激活时，地址转换检测信号的产生被掩码电路掩蔽。 可以防止激活操作和正常行激活信号的失活操作之间的冲突，并且可以稳定地执行内部操作。 提供了一种具有与静态随机存取存储器兼容并且能够稳定地执行内部操作的接口的无刷新的动态半导体存储器件。

公开(公告)号：US06882586B2

公开(公告)日：2005-04-19

申请号：US10267670

申请日：2002-10-10

申请人： Hirotoshi Sato ,  Masaki Tsukude

发明人： Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C29/14 ,  G11C7/00

CPC分类号： G11C29/12015 ,  G11C7/22 ,  G11C11/401 ,  G11C11/406 ,  G11C29/14

摘要： A semiconductor memory device is provided with a memory cell array including memory cells being arranged in a shape of matrix and requiring a refresh operation. In the semiconductor memory device, a control circuit controls a timing of the refresh operation in accordance with an internal signal independently of an external signal and controlling the memory cell array in a non-normal operation mode different from a normal operation mode for writing data into the memory cell array and reading out data from the memory cell array. The control circuit starts the non-normal operation mode in response to a sequence of entry into the non-normal operation mode based on a predetermined first command signal, sets the non-normal operation mode in response to a sequence of setting the non-normal operation mode based on a predetermined second command signal, and thereafter, executes operation of the corresponding non-normal operation mode which is set.

摘要翻译： 半导体存储器件设置有存储单元阵列，其包括以矩阵形状布置并需要刷新操作的存储单元。 在半导体存储装置中，控制电路根据与外部信号无关的内部信号来控制刷新动作的定时，并将存储单元阵列控制在与将数据写入的通常动作模式不同的非正常动作模式 存储单元阵列并从存储单元阵列中读出数据。 控制电路响应于基于预定的第一命令信号进入非正常操作模式的顺序而开始非正常操作模式，响应于非正常设置的顺序设置非正常操作模式 基于预定的第二命令信号进行操作模式，然后执行设定的相应的非正常操作模式的操作。

公开(公告)号：US06737906B2

公开(公告)日：2004-05-18

申请号：US09986871

申请日：2001-11-13

申请人： Minoru Senda ,  Masaki Tsukude

发明人： Minoru Senda ,  Masaki Tsukude

IPC分类号： G05F110

CPC分类号： H02M3/07 ,  H02M2003/071

摘要： In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.

摘要翻译： 在操作中，电荷泵浦电路向内部电压线提供负电荷以便减小负的内部电压。 分压电路根据外部施加到测试模式中的第一输入端子的第一正电压与内部电压之间的差产生控制电压。 比较电路根据外部施加到测试模式中的第二输入端子的第二正电压与控制电压之间的比较结果来操作电荷泵送电路。 第二正电压根据负内部电压的目标值设定。

公开(公告)号：US06693838B2

公开(公告)日：2004-02-17

申请号：US10267753

申请日：2002-10-10

申请人： Tsukasa Hagura ,  Takafumi Takatsuka ,  Masaki Tsukude

发明人： Tsukasa Hagura ,  Takafumi Takatsuka ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A semiconductor memory device such as a pseudo SRAM or the like is provided with a memory cell array being refreshed in accordance with a refresh timing signal having a predetermined refresh period and generated by a refresh timing signal generator circuit. A selector selects a block to hold data in the memory cell array divided into a plurality of blocks in accordance with a predetermined command signal, and a signal generator changes the refresh period according to a number of blocks selected by said selecting means, and generates a refresh timing signal having a changed refresh period and outputs a generated refresh signal.

摘要翻译： 诸如伪SRAM等的半导体存储器件设置有根据具有预定刷新周期并由刷新定时信号发生器电路产生的刷新定时信号进行刷新的存储单元阵列。 选择器根据预定的命令信号选择块以将数据保存在被划分成多个块的数据中，并且信号发生器根据由所述选择装置选择的块的数量来改变刷新周期，并且生成 刷新定时信号具有改变的刷新周期并输出产生的刷新信号。

公开(公告)号：US06194776B1

公开(公告)日：2001-02-27

申请号：US08850111

申请日：1997-05-01

申请人： Teruhiko Amano ,  Masaki Tsukude

发明人： Teruhiko Amano ,  Masaki Tsukude

IPC分类号： H01L2900

CPC分类号： H01L21/823493 ,  H01L21/761 ,  H01L29/1079 ,  H01L29/1087 ,  Y10S257/901

摘要： A semiconductor circuit device having a triple-well structure wherein a predetermined potential level is supplied to a top well without a contact region formed in the top well is disclosed. In an N-type ion implantation step for forming an N-type well region (1) in a P-type semiconductor substrate (5), a mask of a predetermined configuration is used so that ions are not implanted into a region of a portion which is to serve as a bottom portion (1B) of the well region (1). Then, the N-type well region (1) is formed which is shaped such that a portion (6) having P-type properties remains partially in the bottom portion (1B). The P-type portion (6) establishes electrical connection between a P-type well region (2) and the semiconductor substrate (5) to permit the potential applied to a contact region (4) to be supplied to the well region (2) therethrough. The portion (6) may include a plurality of portions (6) which allow uniform potential supply. This structure may be applied to basic cells of a memory cell array block.

摘要翻译： 公开了一种具有三阱结构的半导体电路器件，其中将预定电位电平提供给顶部阱，而不形成在顶部阱中的接触区域。 在用于在P型半导体衬底（5）中形成N型阱区（1）的N型离子注入步骤中，使用预定构造的掩模，使得离子不被注入到部分的区域中 其用作井区（1）的底部（1B）。 然后，形成N型阱区域（1），其形状使得具有P型特性的部分（6）部分地保留在底部（1B）中。 P型部分（6）建立P型阱区（2）和半导体衬底（5）之间的电连接，以允许施加到接触区（4）的电势被提供给阱区（2） 通过。 部分（6）可以包括允许均匀电势供应的多个部分（6）。 该结构可以应用于存储单元阵列块的基本单元。

公开(公告)号：US5917765A

公开(公告)日：1999-06-29

申请号：US951591

申请日：1997-10-16

申请人： Fukashi Morishita ,  Masaki Tsukude

发明人： Fukashi Morishita ,  Masaki Tsukude

IPC分类号： G01R31/28 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  G11C29/50 ,  H01L21/66 ,  G11C13/00

CPC分类号： G11C29/50008 ,  G11C29/028 ,  G11C29/50 ,  G11C5/147 ,  G11C11/401 ,  G11C2029/5004

摘要： A semiconductor integrated circuit device realizing high speed operation and low current consumption and ensure reliability evaluation is provided. Reference voltage generating circuits for generating reference voltages of mutually different voltage levels are provided for power supply pads respectively, and voltage down converters for down converting power supply voltages of corresponding external power supply pads to corresponding reference voltage levels and transmitting the lowered voltages to corresponding internal power supply lines are provided corresponding to respective reference voltage generating circuits. Further, a switching transistor is provided at an output node of the reference voltage generating circuit which is rendered conductive at a stress acceleration mode for connecting the corresponding external power supply pad to the output node of the corresponding reference voltage generating circuit.

摘要翻译： 提供实现高速运行和低电流消耗并确保可靠性评估的半导体集成电路装置。 提供用于产生相互不同电压电平的参考电压的参考电压产生电路，以及用于将相应的外部电源焊盘的电源电压下变换为相应的参考电压电平的降压转换器，并将降低的电压传输到相应的内部 对应于各个参考电压产生电路提供电源线。 此外，开关晶体管设置在基准电压产生电路的输出节点处，其以应力加速模式导通，用于将相应的外部电源焊盘连接到相应的参考电压产生电路的输出节点。

公开(公告)号：US5812490A

公开(公告)日：1998-09-22

申请号：US912200

申请日：1997-08-18

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1051

摘要： An external clock signal ext.CLK applied to an external clock input pad is transferred to two internal clock generation circuits independent from each other through two independent input first stage circuits. An internal clock signal int.CLK1 controlling the operations of row related circuits and column related circuits is supplied by a first clock generation circuit and an internal clock signal int.CLK2 controlling an output buffer circuit is supplied from a second clock generation circuit.

摘要翻译： 施加到外部时钟输入焊盘的外部时钟信号ext.CLK通过两个独立的输入第一级电路彼此独立地传送到两个内部时钟产生电路。 控制行相关电路和列相关电路的操作的内部时钟信号int.CLK1由第一时钟产生电路提供，并且控制输出缓冲器电路的内部时钟信号int.CLK2由第二时钟发生电路提供。

公开(公告)号：US20110199844A1

公开(公告)日：2011-08-18

申请号：US13081821

申请日：2011-04-07

申请人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

发明人： Takeo Miki ,  Seiji Sawada ,  Masaki Tsukude

IPC分类号： G11C8/18 ,  G11C7/06

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A semiconductor memory device for operating in synchronization with a clock is disclosed. The semiconductor includes a memory array having a plurality of memory cells arranged in rows and columns; and a control circuit performing a control, operation to effect row access processing on a selected row and to effect column access processing on column(s). The control being performed in synchronization with a first clock defined by a time of production of the read signal or the write signal according to an externally applied control signal. the control is also performed in synchronization with a second or later clock defined by a latency, to effect the column access processing on a second number of the columns remaining in the burst mode access

摘要翻译： 公开了一种与时钟同步操作的半导体存储器件。 半导体包括具有以行和列排列的多个存储单元的存储器阵列; 以及控制电路，执行控制，对所选择的行进行行访问处理的操作，并对列执行列访问处理。 该控制与根据外部施加的控制信号的读取信号或写入信号的产生时间所限定的第一时钟同步执行。 控制还与由等待时间定义的第二或更迟的时钟同步地执行，以对在突发模式存取中剩余的第二数量的列进行列访问处理

公开(公告)号：US07983103B2

公开(公告)日：2011-07-19

申请号：US12333913

申请日：2008-12-12

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C8/18 ,  G11C11/40615 ,  G11C2211/4061

摘要： A trigger producing circuit provides a trigger signal. A delay circuit receives the trigger signal, and provides a delay signal produced by delaying the trigger signal. A clock counter receives clocks, counts the received clocks for a period from reception of the trigger signal to reception of the delay signal, and provides a result of the counting. A determining circuit stores a relationship between the number of clocks and a latency, and determines the latency corresponding to the result of counting provided from the clock counter. A latency register holds the determined latency. A WAIT control circuit externally provides a WAIT signal based on the latency held in the latency register.

摘要翻译： 触发产生电路提供触发信号。 延迟电路接收触发信号，并提供通过延迟触发信号而产生的延迟信号。 时钟计数器接收时钟，对从接收到触发信号到接收延迟信号的时间段中的接收时钟进行计数，并提供计数结果。 确定电路存储时钟数和等待时间之间的关系，并且确定与从时钟计数器提供的计数结果相对应的等待时间。 延迟寄存器保存所确定的延迟。 WAIT控制电路根据等待时间寄存器中保存的等待时间外部提供WAIT信号。

公开(公告)号：US20080062776A1

公开(公告)日：2008-03-13

申请号：US11976354

申请日：2007-10-24

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C11/40615 ,  G11C2211/4061 ,  G11C2211/4067

摘要： In a DRAM having a complete hidden refresh function, when data refresh is to be carried out in an active mode, a signal for selecting a way is set to an “H” level and then reset to an “L” level at each cycle while the corresponding upper address is designated. When data refresh is to be carried out in a standby mode, the signal for selecting the way is maintained at an “H” level and is not reset to an “L” level while the corresponding upper address is designated. This can reduce the standby current.