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    Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller
    73.
    发明授权
    Apparatus for performing real time caching utilizing an execution quantization timer and an interrupt controller 失效
    用于使用执行量化定时器和中断控制器执行实时高速缓存的装置

    公开(公告)号：US6016531A

    公开(公告)日：2000-01-18

    申请号：US451802

    申请日：1995-05-26

    申请人： Scott W. Rixner ,  Clarence R. Ogilvie

    发明人： Scott W. Rixner ,  Clarence R. Ogilvie

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0802 ,  G06F12/0846

    摘要： A system for managing the flow of real time data streams into a data system cache memory is disclosed. The data system includes a central processing unit or micro controller, with a cache memory, which operates at a relatively fast operating speed, near that of the central processing unit. An interrupt controller is provided as well as a quantization timer that disables the interrupts to the CPU during an execution quantization (EQ) period, and allows the interrupts to pass at an EQ boundary. In operation, the quantization timer controls interrupts to occur only when cache load actions are at a specific quantized time, thus ensuring that a given task in the cache will execute or load for a given quantized length of time, and therefore, the possibility of loading a cache randomly only to execute a few instructions is eliminated.

    摘要翻译： 公开了一种用于管理实时数据流流入数据系统高速缓冲存储器的系统。 数据系统包括中央处理单元或微控制器，具有高速缓冲存储器，其以相对较快的操作速度操作，靠近中央处理单元的操作速度。 提供了中断控制器以及在执行量化（EQ）期间禁止CPU中断的量化定时器，并允许中断通过EQ边界。 在操作中，量化定时器控制中断仅在高速缓存加载动作处于特定量化时间时发生，从而确保高速缓存中的给定任务将在给定的量化长度的时间内执行或加载，并且因此可以加载 消除了随机只执行几个指令的缓存。

    Tree-type multiplexers and methods for configuring the same
    74.
    发明授权
    Tree-type multiplexers and methods for configuring the same 失效
    树型多路复用器及其配置方法

    公开(公告)号：US5243599A

    公开(公告)日：1993-09-07

    申请号：US710623

    申请日：1991-06-05

    申请人： Stephen B. Barrett ,  Clarence R. Ogilvie

    发明人： Stephen B. Barrett ,  Clarence R. Ogilvie

    IPC分类号： H03K17/00 ,  H04J3/04

    CPC分类号： H04J3/047 ,  H03K17/005

    摘要： N stage tree-type mutliplexers having multiple selects and associated processes for configuring the same are disclosed. The basic multiplexer has control signals which are disbursed throughout the tree for high performance multiplexing. Control signals are distributed such that different signals control at least one stage of the N stage tree and such that the signals controlling the selectors in each of the plurality of selector paths from the input stage to the output stage of the tree are unique. As an enhancement, circuitry for buffering the control signals provided to the input stage of the tree can be used to further reduce the capacitive load thereon.

    摘要翻译： 公开了具有多个选择的N级树型多路复用器和用于配置它们的关联过程。 基本的多路复用器具有控制信号，它们遍布整个树进行高性能复用。 分配控制信号，使得不同的信号控制N级树的至少一级，并且使得控制从输入级到树的输出级的多个选择器路径中的每一个中的选择器的信号是唯一的。 作为增强，可以使用用于缓冲提供给树的输入级的控制信号的电路来进一步减小其上的容性负载。

    Adaptive power control using timing canonicals
    75.
    发明授权
    Adaptive power control using timing canonicals 有权
    使用定时规范的自适应功率控制

    公开(公告)号：US09157956B2

    公开(公告)日：2015-10-13

    申请号：US13614564

    申请日：2012-09-13

    申请人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    发明人： Jeanne P. Bickford ,  Eric A. Foreman ,  Peter A. Habitz ,  Jeffrey G. Hemmett ,  Clarence R. Ogilvie ,  Tad J. Wilder ,  Vladimir Zolotov

    IPC分类号： G06F17/50 ,  G01R31/317 ,  G01R31/30

    CPC分类号： G01R31/31718 ,  G01R31/3008

    摘要： A plurality of digital circuits are manufactured from an identical circuit design. A power controller is operatively connected to the digital circuits, and a non-transitory storage medium is operatively connected to the power controller. The digital circuits are classified into different voltage bins, and each of the voltage bins has a current leakage limit. Each of the digital circuits has been previously tested to operate within a corresponding current leakage limit of a corresponding voltage bin into which each of the digital circuits has been classified. The non-transitory storage medium stores boundaries of the voltage bins as speed-binning test data. The power controller controls power-supply signals applied differently for each of the digital circuits based on which bin each of the digital circuit has been classified and the speed-binning test data.

    摘要翻译： 由相同的电路设计制造多个数字电路。 功率控制器可操作地连接到数字电路，并且非瞬时存储介质可操作地连接到功率控制器。 数字电路分为不同的电压箱，每个电压箱都有漏电极限。 已经对每个数字电路进行了测试，以在对应的电压仓的相应的电流泄漏极限内运行，每个数字电路已被分类到该对应的电压仓。 非瞬时存储介质存储电压仓的边界作为速度分组测试数据。 功率控制器控制基于每个数字电路已被分类的每个数字电路不同地施加的电源信号和速度合并测试数据。

    CRITICAL PATH DELAY PREDICTION
    76.
    发明申请
    CRITICAL PATH DELAY PREDICTION 审中-公开
    关键路径延迟预测

    公开(公告)号：US20130041608A1

    公开(公告)日：2013-02-14

    申请号：US13204812

    申请日：2011-08-08

    申请人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Matthew P. Szafir ,  Tad J. Wilder

    发明人： Margaret R. Charlebois ,  Rashmi D. Chatty ,  Christopher D. Hanudel ,  Robert D. Herzl ,  David W. Milton ,  Clarence R. Ogilvie ,  Matthew P. Szafir ,  Tad J. Wilder

    IPC分类号： G06F19/00

    CPC分类号： G06F17/5031

    摘要： Embodiments of the invention provide a method, system, and program product for predicting a delay of a critical path. In one embodiment, the invention provides a method of predicting a delay of at least one critical path of an integrated circuit, the method comprising: determining a delay of at least one ring oscillator on the integrated circuit; and calculating a predicted delay for the at least one critical path delay based on a delay of components of the critical path at a corner condition, a wire delay of the at least one critical path, a delay of the at least one ring oscillator at a corner condition, and the determined delay of the at least one ring oscillator.

    摘要翻译： 本发明的实施例提供了用于预测关键路径的延迟的方法，系统和程序产品。 在一个实施例中，本发明提供了一种预测集成电路的至少一个关键路径的延迟的方法，所述方法包括：确定所述集成电路上的至少一个环形振荡器的延迟; 以及基于角点条件下的关键路径的分量的延迟，所述至少一个关键路径的有线延迟，所述至少一个环形振荡器的延迟在一个 并且确定所述至少一个环形振荡器的延迟。

    Asynchronous interface methods and apparatus
    80.
    发明授权
    Asynchronous interface methods and apparatus 失效
    异步接口方法和设备

    公开(公告)号：US07319729B2

    公开(公告)日：2008-01-15

    申请号：US10605405

    申请日：2003-09-29

    申请人： Seetharam Gundurao ,  Kenneth A. Lauricella ,  Clarence R. Ogilvie ,  Nishant Sharma ,  Richard N. Wilson

    发明人： Seetharam Gundurao ,  Kenneth A. Lauricella ,  Clarence R. Ogilvie ,  Nishant Sharma ,  Richard N. Wilson

    IPC分类号： H04L7/00

    CPC分类号： H03M9/00 ,  H04L7/0041 ,  H04L25/14

    摘要： In a first aspect of the invention, a first method is provided for aligning signals from a first receiver located in a first clock domain to a second receiver located in a second clock domain. The first method includes the steps of creating a programmable delay element between the first and second receivers, and selectively adding delay via the programmable delay element to the signals until the signals are aligned. Numerous other aspects are provided.

    摘要翻译： 在本发明的第一方面，提供了一种第一种方法，用于将来自位于第一时钟域中的第一接收机的信号对准位于第二时钟域中的第二接收机。 第一种方法包括以下步骤：在第一和第二接收机之间创建可编程延迟元件，并且经由可编程延迟元件选择性地将延迟添加到信号中直到信号被对准。 提供了许多其他方面。