METHOD FOR MANUFACTURING A BORONIC ACID ESTER COMPOUND
    72.
    发明申请
    METHOD FOR MANUFACTURING A BORONIC ACID ESTER COMPOUND 失效
    制备硼酸酯化合物的方法

    公开(公告)号:US20120123122A1

    公开(公告)日:2012-05-17

    申请号:US13142536

    申请日:2009-03-24

    IPC分类号: C07F5/04

    CPC分类号: C07F5/025

    摘要: The present invention relates to a method for manufacturing a boronic acid ester compound, characterized by reacting an aryl halide compound and a diboron ester compound in the presence of a nitrogen-containing organic base, a nickel catalyst, a phosphine compound and a solvent. According to the manufacturing method of the present invention, even if a nickel catalyst is used as the catalyst, a desired boronic acid ester compound can be obtained in a sufficiently high yield. Furthermore, even if aryl chloride or aryl bromide having relatively low price and low reactivity, was used as the aryl halide compound, a desired boronic acid ester compound can be obtained in a sufficiently high yield.

    摘要翻译: 硼酸酯化合物的制造方法技术领域本发明涉及硼酸酯化合物的制造方法,其特征在于,在含氮有机碱,镍催化剂,膦化合物和溶剂的存在下,使芳基卤化合物与二硼酸酯化合物反应。 根据本发明的制造方法,即使使用镍催化剂作为催化剂,也能以足够高的收率获得所需的硼酸酯化合物。 此外,即使使用价格低廉,反应性低的芳基氯或芳基溴作为芳基卤化合物,可以以足够高的收率得到所需的硼酸酯化合物。

    ANALYSIS DEVICE, AND ANALYSIS APPARATUS AND METHOD USING THE SAME
    74.
    发明申请
    ANALYSIS DEVICE, AND ANALYSIS APPARATUS AND METHOD USING THE SAME 有权
    分析装置,以及分析装置和使用该装置的方法

    公开(公告)号:US20100221741A1

    公开(公告)日:2010-09-02

    申请号:US12681493

    申请日:2008-10-03

    IPC分类号: G01N33/53 C12M1/34 C12Q1/02

    摘要: An analysis device includes: a separation cavity 18 for separating a test liquid into a solution component and a solid component by using a centrifugal force; a higher specific gravity component quantitative cavity 23 for holding a portion of the separated solid component which has been transferred; a sample solution overflow cavity 22 arranged between the higher specific gravity component quantitative cavity 23 and the separation cavity 18 and connected to a connecting channel 21 for transporting the sample liquid from the separation cavity 18; and a capillary cavity 19 formed in the separation cavity 18 for temporarily holding a separated solution component (blood plasma) in the separation cavity 18. A blood plasma component 57a remaining in the separation cavity 18 is trapped by the capillary cavity 19.

    摘要翻译: 分析装置包括:分离腔18,用于通过离心力将测试液体分离成溶液成分和固体成分; 用于保持被转移的分离的固体成分的一部分的较高比重分量定量腔23; 布置在较高比重分量定量空腔23和分离腔18之间的样品溶液溢出腔22,并连接到用于从分离腔18输送样品液体的连接通道21; 以及形成在分离腔18中的毛细管腔19,用于在分离腔18中临时保持分离的溶液成分(血浆)。留在分离腔18中的血浆组分57a被毛细管腔19捕获。

    CRYOGENIC SYSTEM
    75.
    发明申请
    CRYOGENIC SYSTEM 有权
    低温系统

    公开(公告)号:US20070271933A1

    公开(公告)日:2007-11-29

    申请号:US11026153

    申请日:2005-01-03

    申请人: Takashi Miki

    发明人: Takashi Miki

    IPC分类号: F25B19/00 F25B9/00

    摘要: A cryogenic system includes a space formed between a cooling stage of a cryocooler unit and an element to be cooled, and a thermal joint placed in the space, wherein the thermal joint is composed of a substance that has a melting point higher than the cooling temperature of the element to be cooled and that is in a liquid or gaseous state at room temperature and atmospheric pressure. The cryogenic system can achieve reproducible and excellent thermal contact at a cooling stage without applying a large mechanical stress to a cryocooler unit structure.

    摘要翻译: 低温系统包括在冷却器单元的冷却段和要冷却的元件之间形成的空间和放置在该空间中的热接头,其中,热接头由熔点高于冷却温度的物质构成 的待冷却元件,并且在室温和大气压下处于液态或气态。 低温系统可以在冷却阶段实现可重现和优异的热接触,而不会对低温冷却器单元结构施加大的机械应力。

    Semiconductor memory device
    76.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号:US20070195578A1

    公开(公告)日:2007-08-23

    申请号:US11707157

    申请日:2007-02-16

    IPC分类号: G11C11/22

    CPC分类号: G11C11/22

    摘要: A memory cell array is composed of a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a capacitor having a plate electrode connected to a common cell plate and a storage electrode; and a transistor provided between the storage electrode of the capacitor and a bit line, with a gate connected to a word line. A first amplifier amplifies an I/O line pair to a first voltage and a second voltage higher than the first voltage. A second amplifier amplifies a bit line pair to the first voltage and a third voltage higher than the second voltage. A switch element switches the connection relationship between the I/O line pair and the bit line pair among a connected state, a disconnected state and a transmission limited state in which the potential transmitted is limited.

    摘要翻译: 存储单元阵列由以矩阵排列的多个存储单元组成。 每个存储单元包括:具有连接到公共单元板和存储电极的平板电极的电容器; 以及设置在电容器的存储电极和位线之间的晶体管,栅极连接到字线。 第一放大器将I / O线对放大到高于第一电压的第一电压和第二电压。 第二放大器将位线对放大到第一电压和高于第二电压的第三电压。 开关元件在连接状态,断开状态和限制发送电位的发送限制状态之间切换I / O线对与位线对之间的连接关系。

    Semiconductor memory device
    79.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US20060171246A1

    公开(公告)日:2006-08-03

    申请号:US11344199

    申请日:2006-02-01

    IPC分类号: G11C8/00

    摘要: Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译: 提供了与SRAM兼容的半导体存储器件,并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时,对存储器核心6的访问开始。 同时,接收外部写入使能信号XWE和外部地址信号ADD,并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时,根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor memory device
    80.
    发明申请
    Semiconductor memory device 审中-公开
    半导体存储器件

    公开(公告)号:US20060113581A1

    公开(公告)日:2006-06-01

    申请号:US11289441

    申请日:2005-11-30

    IPC分类号: H01L29/94

    摘要: A semiconductor memory device having a memory cell array in which plural memory transistors and plural memory call capacitors, which are components of memory cells, are arranged, comprises a first wiring layer formed on the memory cell array, and a second wiring layer formed above the first wiring layer, wherein a wiring density of the first wiring layer on the memory cell array is higher than a wiring density of the second wiring layer on the memory cell array. Therefore, a hydrogen barrier property for the capacitors is improved, and an adverse effect due to stress applied to the capacitors is reduced, thereby suppressing deterioration of capacitor characteristics.

    摘要翻译: 一种具有存储单元阵列的半导体存储器件,其中布置有作为存储单元的组件的多个存储晶体管和多个存储器调用电容器,包括形成在存储单元阵列上的第一布线层和形成在存储单元阵列上方的第二布线层 第一布线层,其中存储单元阵列上的第一布线层的布线密度高于存储单元阵列上的第二布线层的布线密度。 因此,电容器的氢阻挡性提高,并且由于施加到电容器的应力引起的不利影响降低,从而抑制电容器特性的劣化。