公开(公告)号：US08772059B2

公开(公告)日：2014-07-08

申请号：US13430631

申请日：2012-03-26

Applicant: Yu Yang ,  Krishnaswamy Ramkumar

Inventor： Yu Yang ,  Krishnaswamy Ramkumar

IPC: H01L21/66

CPC classification number: H01L29/792 ,  H01L22/14 ,  H01L29/66833

Abstract: Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages.

Abstract translation: 描述了用于确定包括电荷存储层和隧穿层的非易失性存储晶体管的操作特性的结构和方法的实施例。 在一个实施例中，该方法包括：在衬底上形成包括氮化隧道层和覆盖隧道层的电荷存储层的结构，该隧穿层包括与隧道层相邻的第一电荷存储层和第二电荷 覆盖在第一电荷存储层上的第一电荷存储层，其中第一电荷存储层通过包含氧化物的反隧道层与第二电荷存储层分离; 在电荷存储层上沉积正电荷并确定第一电压以建立通过电荷存储层和隧道层的第一泄漏电流; 在电荷存储层上沉积负电荷并确定第二电压以建立通过电荷存储层和隧穿层的第二泄漏电流; 以及通过计算所述第一和第二电压之间的差来确定差分电压。

公开(公告)号：US08710579B1

公开(公告)日：2014-04-29

申请号：US13551237

申请日：2012-07-17

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  G11C16/04 ,  H01L21/022 ,  H01L21/02323 ,  H01L27/11563 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device comprises a split charge-trapping region comprising two nitride layers with charge traps distributed therein, the two nitride layers separated by one or more oxide layers. The two nitride layers include a first nitride layer closer to a substrate over which the split charge-trapping region is formed, and a second nitride layer on the other side of the one or more oxide layers. The second nitride layer comprises a majority of the charge traps. Other embodiments are also described.

Abstract translation: 提供半导体器件及其制造方法。 在一个实施例中，半导体器件包括分离的电荷捕获区域，其包括分布有电荷陷阱的两个氮化物层，两个氮化物层由一个或多个氧化物层分隔开。 两个氮化物层包括更靠近其上形成有分离电荷捕获区的衬底的第一氮化物层和在一个或多个氧化物层的另一侧上的第二氮化物层。 第二氮化物层包括大部分电荷阱。 还描述了其它实施例。

公开(公告)号：US08679927B2

公开(公告)日：2014-03-25

申请号：US12185751

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US08536640B2

公开(公告)日：2013-09-17

申请号：US11904474

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

IPC: H01L29/792

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

公开(公告)号：US20130175600A1

公开(公告)日：2013-07-11

申请号：US13431069

申请日：2012-03-27

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/785 ,  H01L29/7926

Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

Abstract translation: 描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。 通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离 从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。 还公开了其他实施例。

公开(公告)号：US20130175599A1

公开(公告)日：2013-07-11

申请号：US13430631

申请日：2012-03-26

Applicant: Yu Yang ,  Krishnaswamy Ramkumar

Inventor： Yu Yang ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/66

CPC classification number: H01L29/792 ,  H01L22/14 ,  H01L29/66833

Abstract: Embodiments of structures and methods for determining operating characteristics of a non-volatile memory transistor comprising a charge-storage-layer and a tunneling-layer are described. In one embodiment, the method comprises: forming on a substrate a structure including a nitrided tunneling-layer and a charge-storage-layer overlying the tunneling-layer comprising a first charge-storage layer adjacent to the tunneling-layer, and a second charge-storage layer overlying the first charge-storage layer, wherein the first charge-storage layer is separated from the second charge-storage layer by a anti-tunneling layer comprising an oxide; depositing a positive charge on the charge-storage-layer and determining a first voltage to establish a first leakage current through the charge-storage-layer and the tunneling-layer; depositing a negative charge on the charge-storage-layer and determining a second voltage to establish a second leakage current through the charge-storage-layer and the tunneling-layer; and determining a differential voltage by calculating a difference between the first and second voltages.

Abstract translation: 描述了用于确定包括电荷存储层和隧穿层的非易失性存储晶体管的操作特性的结构和方法的实施例。 在一个实施例中，该方法包括：在衬底上形成包括氮化隧道层和覆盖隧道层的电荷存储层的结构，该隧穿层包括与隧道层相邻的第一电荷存储层和第二电荷 覆盖在第一电荷存储层上的第一电荷存储层，其中第一电荷存储层通过包含氧化物的反隧道层与第二电荷存储层分离; 在电荷存储层上沉积正电荷并确定第一电压以建立通过电荷存储层和隧道层的第一泄漏电流; 在电荷存储层上沉积负电荷并确定第二电压以建立通过电荷存储层和隧穿层的第二泄漏电流; 以及通过计算所述第一和第二电压之间的差来确定差分电压。

公开(公告)号：US08093128B2

公开(公告)日：2012-01-10

申请号：US12125864

申请日：2008-05-22

Applicant: William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

Inventor： William W. C. Koutny, Jr. ,  Sam Geha ,  Igor Kouznetsov ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

公开(公告)号：US08088683B2

公开(公告)日：2012-01-03

申请号：US12080166

申请日：2008-03-31

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/4763

CPC classification number: H01L21/28282 ,  H01L21/3145

Abstract: Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

Abstract translation: 重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。 在一个具体实施方案中，进行包括NH 3或ND 3环境，随后是N 2 O或NO环境的两步退火。 在一个实施例中，采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层，这在沉积过程中具有非常高的特性。 在特定实施例中，顺序沉积 - 退火操作提供退火的第一介电层，第二介电层可以在其上基本上保持不退火。

公开(公告)号：US07880219B2

公开(公告)日：2011-02-01

申请号：US11904470

申请日：2007-09-26

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L29/792 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/045 ,  H01L29/42324

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract translation: 描述了一种非易失性电荷陷阱存储器件及其形成方法。 该器件包括具有<100>晶面取向的沟道长度的沟道区。 沟道区域位于一对源极区和漏极区之间，栅极堆叠设置在沟道区的上方。

公开(公告)号：US20090020831A1

公开(公告)日：2009-01-22

申请号：US11904474

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

Inventor： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  William W. Koutny

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/792

Abstract: A nonvolatile charge trap memory device with deuterium passivation of charge traps and method of manufacture. Deuterated gate layer, deuterated gate cap layer and deuterated spacers are employed in various combinations to encapsulate the device with deuterium sources proximate to the interfaces within the gate stack and on the surface of the gate stack where traps may be present.

Abstract translation: 具有充电阱的氘钝化的非挥发性电荷陷阱存储器件及其制造方法。 氘代栅极层，氘化栅极覆盖层和氘代间隔物被采用各种组合，以将器件与邻近栅极堆叠内的界面的氘源以及可能存在阱的栅极堆叠的表面封装。