公开(公告)号：US20050078537A1

公开(公告)日：2005-04-14

申请号：US10676862

申请日：2003-09-30

申请人： Kenneth So ,  Luca Fasoli ,  Bendik Kleveland

发明人： Kenneth So ,  Luca Fasoli ,  Bendik Kleveland

IPC分类号： G11C7/04

CPC分类号： G11C5/147 ,  G11C5/143 ,  G11C7/04 ,  G11C7/12 ,  G11C8/08 ,  G11C13/0069

摘要： The preferred embodiments described herein relate to a method and system for temperature compensation for memory cells with temperature-dependent behavior. In one preferred embodiment, at least one of a first temperature-dependent reference voltage comprising a negative temperature coefficient and a second temperature-dependent reference voltage comprising a positive temperature coefficient is generated. One of a wordline voltage and a bitline voltage is generated from one of the at least one of the first and second temperature-dependent reference voltages. The other of the wordline and bitline voltages is generated, and the wordline and bitline voltages are applied across a memory cell. Other methods and systems are disclosed for sensing a memory cell comprising temperature-dependent behavior, and each of the preferred embodiments can be used alone or in combination with one another.

摘要翻译： 本文描述的优选实施例涉及用于具有温度依赖行为的存储器单元的温度补偿的方法和系统。 在一个优选实施例中，产生包括负温度系数和包括正温度系数的第二温度依赖参考电压的第一温度依赖性参考电压中的至少一个。 从第一和第二温度依赖参考电压中的至少一个之一产生字线电压和位线电压之一。 产生字线和位线电压中的另一个，并且字线和位线电压跨越存储器单元施加。 公开了用于感测包含温度依赖行为的存储单元的其它方法和系统，并且每个优选实施例可以单独使用或彼此组合使用。

公开(公告)号：US08982597B2

公开(公告)日：2015-03-17

申请号：US13362320

申请日：2012-01-31

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C5/02 ,  G11C16/24 ,  G11C13/00

CPC分类号： G11C16/24 ,  G11C13/0028

摘要： The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

摘要翻译： 该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。 每个一个或多个块的集合包括一组本地数据线。 每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。 每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。 每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

公开(公告)号：US08279650B2

公开(公告)日：2012-10-02

申请号：US12563139

申请日：2009-09-20

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C5/02 ,  G11C11/00 ,  G11C5/06

CPC分类号： G11C8/12 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selections circuits can change their selections independently of each other. For example, a memory operation is performed concurrently on a first non-volatile storage element of each group of a plurality of groups of non-volatile storage elements. Completion of the memory operation for the first non-volatile storage element of each group is independently detected. A memory operation on a second non-volatile storage element of each group is independently commenced for each group upon independently detecting completion of the memory operation for the first non-volatile storage element of the respective group.

摘要翻译： 存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。 每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。 每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。 为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。 例如，在多组非易失性存储元件的每组的第一非易失性存储元件上同时执行存储器操作。 独立检测每组的第一非易失性存储元件的存储器操作的完成。 在独立地检测对相应组的第一非易失性存储元件的存储器操作的完成时，对于每个组，在每个组的第二非易失性存储元件上的存储器操作被独立地开始。

公开(公告)号：US08223525B2

公开(公告)日：2012-07-17

申请号：US12638719

申请日：2009-12-15

申请人： Gopinath Balakrishnan ,  Jeffrey Koon Yee Lee ,  Yuheng Zhang ,  Tz-Yi Liu ,  Luca Fasoli

发明人： Gopinath Balakrishnan ,  Jeffrey Koon Yee Lee ,  Yuheng Zhang ,  Tz-Yi Liu ,  Luca Fasoli

IPC分类号： G11C5/06

CPC分类号： G11C5/025 ,  B82Y10/00 ,  G11C5/02 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/025 ,  G11C17/16 ,  G11C2213/19 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/34 ,  G11C2213/71

摘要： A non-volatile storage device includes a substrate, a monolithic three-dimensional memory array of non-volatile storage elements arranged above a portion of the substrate, a plurality of sense amplifiers in communication with the non-volatile storage elements, a plurality of temporary storage devices in communication with the sense amplifiers, a page register in communication with the temporary storage devices, and one or more control circuits. The one or more control circuits are in communication with the page register, the temporary storage devices and the sense amplifiers. The sense amplifiers are arranged on the substrate underneath the monolithic three-dimensional memory array. The temporary storage devices are arranged on the substrate underneath the monolithic three-dimensional memory array. The page register is arranged on the substrate in an area that is not underneath the monolithic three-dimensional memory array. Data read from the non-volatile storage elements by the sense amplifiers is transferred to the temporary storage devices and then to the page register in response to the one or more control circuits. Data to be programmed into the non-volatile storage elements is transferred to the temporary storage devices from the page register in response to the one or more control circuits.

摘要翻译： 非易失性存储装置包括衬底，布置在衬底的一部分上方的非易失性存储元件的单片三维存储器阵列，与非易失性存储元件通信的多个读出放大器，多个临时 与读出放大器通信的存储装置，与临时存储装置通信的页寄存器，以及一个或多个控制电路。 一个或多个控制电路与页寄存器，临时存储设备和读出放大器通信。 读出放大器布置在单片三维存储器阵列下方的衬底上。 临时存储装置布置在单片三维存储器阵列下面的衬底上。 页面寄存器在不在单片三维存储器阵列下方的区域中布置在基板上。 由感测放大器从非易失性存储元件读取的数据响应于一个或多个控制电路传送到临时存储设备，然后传送到页寄存器。 要编程到非易失性存储元件中的数据响应于一个或多个控制电路从页寄存器传送到临时存储设备。

公开(公告)号：US20120091427A1

公开(公告)日：2012-04-19

申请号：US12904802

申请日：2010-10-14

申请人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

发明人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

IPC分类号： H01L45/00 ,  H01L21/02

CPC分类号： H01L27/2481 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

摘要翻译： 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。

公开(公告)号：US08130528B2

公开(公告)日：2012-03-06

申请号：US12410648

申请日：2009-03-25

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/00

CPC分类号： G11C16/24 ,  G11C13/0028

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

摘要翻译： 存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。 块被分组成海湾。 存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。 每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。 该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。 每个一个或多个块的集合包括一组本地数据线。 每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。 每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。 每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

公开(公告)号：US20110305071A1

公开(公告)日：2011-12-15

申请号：US13217235

申请日：2011-08-24

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/1078 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.

摘要翻译： 非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开 信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时 信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。 对控制线进行充电导致相应的非易失性存储元件经历程序操作。 在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

公开(公告)号：US08027209B2

公开(公告)日：2011-09-27

申请号：US12563140

申请日：2009-09-20

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C7/22

CPC分类号： G11C7/1078 ,  G11C7/12 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnects the signal driver from the first control line while the first control line remains charged from the signal driver, connects the signal driver to a second control line that is connected to a second non-volatile storage element, charges the second control line using the signal driver while the signal driver is connected to the second control line, and disconnects the signal driver from the second control line. Charging the control lines causes the respective non-volatile storage elements to experience a program operation. The disconnecting of the signal driver from the first control line, the connecting the signal driver to the second control line and the charging of the second control line are performed without waiting for the first non-volatile storage element's program operation to complete.

摘要翻译： 非易失性存储系统将信号驱动器连接到连接到第一非易失性存储元件的第一控制线，当信号驱动器连接到第一控制线时，使用信号驱动器对第一控制线充电，断开 信号驱动器，而第一控制线保持从信号驱动器充电，将信号驱动器连接到连接到第二非易失性存储元件的第二控制线，使用信号驱动器对第二控制线进行充电，同时 信号驱动器连接到第二控制线，并且将信号驱动器与第二控制线断开。 对控制线进行充电导致相应的非易失性存储元件经历程序操作。 在不等待第一非易失性存储元件的程序操作完成的情况下，执行信号驱动器与第一控制线的断开，将信号驱动器连接到第二控制线和第二控制线的充电。

公开(公告)号：US20110141832A1

公开(公告)日：2011-06-16

申请号：US12638729

申请日：2009-12-15

申请人： Gopinath Balakrishnan ,  Luca Fasoli ,  Tz-Yi Liu ,  Yuheng Zhang ,  Yan Li

发明人： Gopinath Balakrishnan ,  Luca Fasoli ,  Tz-Yi Liu ,  Yuheng Zhang ,  Yan Li

IPC分类号： G11C11/416 ,  G11C7/10

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C13/0007 ,  G11C13/0061 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0076 ,  G11C2013/0085 ,  G11C2213/71

摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

摘要翻译： 非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。 在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。 不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。 一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

公开(公告)号：US20100107022A1

公开(公告)日：2010-04-29

申请号：US12400091

申请日：2009-03-09

申请人： Aldo Bottelli ,  Luca Fasoli

发明人： Aldo Bottelli ,  Luca Fasoli

IPC分类号： G06F12/00 ,  G11C29/08 ,  G06F11/26

CPC分类号： G11C29/812 ,  G11C29/802 ,  G11C29/82

摘要： A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.

摘要翻译： 用于识别存储设备中的存储元件的不良页面的技术。 为一个或多个页面的每个页面组提供标志字节，其指示页面组是否正常。 根据标志字节中的位位置，所选页组的标志字节还指示较大的页组是否健康。 坏页识别过程包括以选定的粒度读取标志字节，以便不读取所有标志字节。 可选地，当将更大的页组组识别为具有至少一个坏页时，下钻过程读取较小组页组的标志字节。 这允许识别坏页组并且标记更加特异性。 标志字节的冗余副本可以存储在存储设备的不同位置。 多数投票过程为每个位分配一个值。