公开(公告)号：US07996736B2

公开(公告)日：2011-08-09

申请号：US12400091

申请日：2009-03-09

申请人： Aldo Bottelli ,  Luca Fasoli

发明人： Aldo Bottelli ,  Luca Fasoli

IPC分类号： G11C29/00 ,  G06F13/00 ,  G06F9/26

CPC分类号： G11C29/812 ,  G11C29/802 ,  G11C29/82

摘要： A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.

摘要翻译： 用于识别存储设备中的存储元件的不良页面的技术。 为一个或多个页面的每个页面组提供标志字节，其指示页面组是否正常。 根据标志字节中的位位置，所选页组的标志字节还指示较大的页组是否健康。 坏页识别过程包括以选定的粒度读取标志字节，以便不读取所有标志字节。 可选地，当将更大的页组组识别为具有至少一个坏页时，下钻过程读取较小组页组的标志字节。 这允许识别坏页组并且标记更加特异性。 标志字节的冗余副本可以存储在存储设备的不同位置。 多数投票过程为每个位分配一个值。

公开(公告)号：US07966532B2

公开(公告)日：2011-06-21

申请号：US12414935

申请日：2009-03-31

申请人： Aldo Bottelli ,  Luca Fasoli ,  Doug Sojourner

发明人： Aldo Bottelli ,  Luca Fasoli ,  Doug Sojourner

IPC分类号： G11C29/00

CPC分类号： G11C29/812 ,  G11C29/802 ,  G11C29/82

摘要： Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.

摘要翻译： 根据当前正在被访问的一组存储元件，例如在读取或写入操作中，在存储器件中选择性地检索列冗余数据。 存储器设备被组织成诸如逻辑块的存储元件组，其中列冗余数据从非易失性存储位置加载到正被访问的一个或多个特定块的易失性存储位置。 易失性存储位置仅需要足够大以存储当前数据条目。 可以基于期望的最大缺陷数量和期望的修复概率来配置列冗余数据同时加载的存储元件组的大小。 在制造生命周期中，随着制造工艺和材料的改进，缺陷数量的减少可以增加组件的尺寸。

公开(公告)号：US20100107004A1

公开(公告)日：2010-04-29

申请号：US12414935

申请日：2009-03-31

申请人： Aldo Bottelli ,  Luca Fasoli ,  Doug Sojourner

发明人： Aldo Bottelli ,  Luca Fasoli ,  Doug Sojourner

IPC分类号： G06F11/20 ,  G06F12/00 ,  G06F12/16 ,  G06F12/02

CPC分类号： G11C29/812 ,  G11C29/802 ,  G11C29/82

摘要： Column redundancy data is selectively retrieved in a memory device according to a set of storage elements which is currently being accessed, such as in a read or write operation. The memory device is organized into sets of storage elements such as logical blocks, where column redundancy data is loaded from a non-volatile storage location to a volatile storage location for one or more particular blocks which are being accessed. The volatile storage location need only be large enough to store the current data entries. The size of the set of storage elements for which column redundancy data is concurrently loaded can be configured based on an expected maximum number of defects and a desired repair probability. During a manufacturing lifecycle, the size of the set can be increased as the number of defects is reduced due to improvements in manufacturing processes and materials.

摘要翻译： 根据当前正在被访问的一组存储元件，例如在读取或写入操作中，在存储器件中选择性地检索列冗余数据。 存储器设备被组织成诸如逻辑块的存储元件组，其中列冗余数据从非易失性存储位置加载到正被访问的一个或多个特定块的易失性存储位置。 易失性存储位置仅需要足够大以存储当前数据条目。 可以基于期望的最大缺陷数量和期望的修复概率来配置列冗余数据同时加载的存储元件组的大小。 在制造生命周期中，随着制造工艺和材料的改进，缺陷数量的减少可以增加组件的尺寸。

公开(公告)号：US20100107022A1

公开(公告)日：2010-04-29

申请号：US12400091

申请日：2009-03-09

申请人： Aldo Bottelli ,  Luca Fasoli

发明人： Aldo Bottelli ,  Luca Fasoli

IPC分类号： G06F12/00 ,  G11C29/08 ,  G06F11/26

CPC分类号： G11C29/812 ,  G11C29/802 ,  G11C29/82

摘要： A technique for identifying bad pages of storage elements in a memory device. A flag byte is provided for each page group of one or more pages which indicates whether the page group is healthy. Flag bytes of selected page groups also indicate whether larger sets of page groups are healthy, according to bit positions in the flag bytes. A bad page identification process includes reading the flag bytes with a selected granularity so that not all flag bytes are read. Optionally, a drill down process reads flag bytes for smaller sets of page groups when a larger set of page groups is identified as having at least one bad page. This allows the bad page groups to be identified and marked with greater specificity. Redundant copies of flag bytes may be stored in different locations of the memory device. A majority vote process assigns a value to each bit.

摘要翻译： 用于识别存储设备中的存储元件的不良页面的技术。 为一个或多个页面的每个页面组提供标志字节，其指示页面组是否正常。 根据标志字节中的位位置，所选页组的标志字节还指示较大的页组是否健康。 坏页识别过程包括以选定的粒度读取标志字节，以便不读取所有标志字节。 可选地，当将更大的页组组识别为具有至少一个坏页时，下钻过程读取较小组页组的标志字节。 这允许识别坏页组并且标记更加特异性。 标志字节的冗余副本可以存储在存储设备的不同位置。 多数投票过程为每个位分配一个值。

公开(公告)号：US08841648B2

公开(公告)日：2014-09-23

申请号：US12904802

申请日：2010-10-14

申请人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

发明人： Yung-Tin Chen ,  Andrei Mihnea ,  Roy E. Scheuerlein ,  Luca Fasoli

IPC分类号： H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  G11C13/00 ,  G11C11/56

CPC分类号： H01L27/2481 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/55 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608

摘要： In some embodiments, a memory array is provided that includes (1) a first memory cell having (a) a first conductive line; (b) a first bipolar storage element formed above the first conductive line; and (c) a second conductive line formed above the first bipolar storage element; and (2) a second memory cell formed above the first memory cell and having (a) a second bipolar storage element formed above the second conductive line; and (b) a third conductive line formed above the second bipolar storage element. The first and second memory cells share the second conductive line; the first bipolar storage element has a first storage element polarity orientation within the first memory cell; the second bipolar storage element has a second storage element polarity orientation within the second memory cell; and the second storage element polarity orientation is opposite the first storage element polarity orientation. Numerous other aspects are provided.

摘要翻译： 在一些实施例中，提供了一种存储器阵列，其包括（1）具有（a）第一导电线的第一存储器单元; （b）形成在第一导线之上的第一双极存储元件; 和（c）形成在所述第一双极存储元件上方的第二导线; 以及（2）形成在所述第一存储单元上方的第二存储单元，并且具有（a）形成在所述第二导线上方的第二双极存储元件; 和（b）形成在第二双极存储元件上方的第三导线。 第一和第二存储单元共享第二导线; 第一双极存储元件在第一存储单元内具有第一存储元件极性取向; 所述第二双极存储元件在所述第二存储单元内具有第二存储元件极性取向; 并且第二存储元件极性取向与第一存储元件极性取向相反。 提供了许多其他方面。

公开(公告)号：US08638586B2

公开(公告)日：2014-01-28

申请号：US13479145

申请日：2012-05-23

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C5/02

CPC分类号： G11C8/12 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

公开(公告)号：US08358528B2

公开(公告)日：2013-01-22

申请号：US13079613

申请日：2011-04-04

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C16/24 ,  G11C13/0028

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. The blocks are grouped into bays. The storage system includes array lines of a first type in communication with storage elements, array lines of a second type in communication with storage elements, and sense amplifiers. Each block is geographically associated with two sense amplifiers and all blocks of a particular bay share a group of sense amplifiers associated with the blocks of the particular bay. The system includes multiple sets of local data lines in one or more routing metal layers below the three-dimensional memory array and multiple sets of global data lines in one or more top metal layers above the three-dimensional memory array. Each set of one or more blocks include one set of the local data lines. Each bay includes one set of global data lines that connect to the group of sense amplifiers associated with the blocks of the respective bay. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines of the first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines associated with a respective bay.

摘要翻译： 存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。 块被分组成海湾。 存储系统包括与存储元件通信的第一类型的阵列线，与存储元件通信的第二类型的阵列线和读出放大器。 每个块在地理上与两个读出放大器相关联，并且特定间隔的所有块共享与特定间隔的块相关联的一组读出放大器。 该系统在三维存储器阵列下面的一个或多个路由金属层中的多组本地数据线和在三维存储器阵列上方的一个或多个顶部金属层中的多组全局数据线。 每个一个或多个块的集合包括一组本地数据线。 每个托架包括一组全局数据线，其连接到与相应托架的块相关联的读出放大器组。 每个块包括用于选择性地将第一类型的阵列线的子集耦合到相应的本地数据线的第一选择电路的子集。 每个块包括用于选择性地将各个本地数据线的子集耦合到与相应的间隔相关联的全局数据线的第二选择电路的子集。

公开(公告)号：US20120257433A1

公开(公告)日：2012-10-11

申请号：US13479145

申请日：2012-05-23

申请人： Tianhong Yan ,  Luca Fasoli

发明人： Tianhong Yan ,  Luca Fasoli

IPC分类号： G11C5/02

CPC分类号： G11C8/12 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066

摘要： A storage system includes a three-dimensional memory array that has multiple layers of non-volatile storage elements grouped into blocks. Each block includes a subset of first selection circuits for selectively coupling a subset of array lines (e.g. bit lines) of a first type to respective local data lines. Each block includes a subset of second selection circuits for selectively coupling a subset of the respective local data lines to global data lines that are connected to control circuitry. To increase the performance of memory operations, the second selection circuits can change their selections independently of each other.

摘要翻译： 存储系统包括具有分组成块的多层非易失性存储元件的三维存储器阵列。 每个块包括用于选择性地将第一类型的阵列线（例如位线）的子集耦合到相应的本地数据线的第一选择电路的子集。 每个块包括用于选择性地将各个本地数据线的子集耦合到连接到控制电路的全局数据线的第二选择电路的子集。 为了提高存储器操作的性能，第二选择电路可以彼此独立地改变它们的选择。

公开(公告)号：US08213243B2

公开(公告)日：2012-07-03

申请号：US12638729

申请日：2009-12-15

申请人： Gopinath Balakrishnan ,  Luca Fasoli ,  Tz-Yi Liu ,  Yuheng Zhang ,  Yan Li

发明人： Gopinath Balakrishnan ,  Luca Fasoli ,  Tz-Yi Liu ,  Yuheng Zhang ,  Yan Li

IPC分类号： G11C7/00

CPC分类号： G11C13/0069 ,  G11C5/02 ,  G11C13/0007 ,  G11C13/0061 ,  G11C17/165 ,  G11C17/18 ,  G11C2013/0076 ,  G11C2013/0085 ,  G11C2213/71

摘要： A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

摘要翻译： 非易失性存储系统包括在编程页面（或其他单元）数据时跳过编程周期的技术。 在对页面（或其他单元）数据的当前子集进行编程时，系统将评估页面（或其他单元）的下一个子集是否应编程为非易失性存储元素或跳过。 不应被跳过的页面（或其他单元）的子集被编程到非易失性存储元件中。 一些实施例包括将适当数据传送到临时锁存器/寄存器，以准备编程，同时评估是编程还是跳过编程。

公开(公告)号：US08050109B2

公开(公告)日：2011-11-01

申请号：US12538492

申请日：2009-08-10

申请人： Thomas Yan ,  Luca Fasoli ,  Roy E Scheuerlein

发明人： Thomas Yan ,  Luca Fasoli ,  Roy E Scheuerlein

IPC分类号： G11C7/10

CPC分类号： G11C7/18 ,  G11C13/004 ,  G11C16/24 ,  G11C2029/0411 ,  G11C2213/71 ,  G11C2213/72

摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.

摘要翻译： 非易失性存储器核心包括一个或多个存储器空间。 每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。 在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。 在存储器操作期间，存储器块被转换为活动状态和非活动状态。 将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一个存储块之间的电荷共享成为可能。 这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。