公开(公告)号：US11620245B2

公开(公告)日：2023-04-04

申请号：US17503392

申请日：2021-10-18

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

IPC: G06F13/28 ,  G06F3/06

Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.

公开(公告)号：US20220350756A1

公开(公告)日：2022-11-03

申请号：US17306033

申请日：2021-05-03

Applicant: Mellanox Technologies LTD.

Inventor： Idan Burstein ,  Ilan Pardo ,  Yamin Friedman ,  Michael Cotsford ,  Mark Rosenbluth ,  Hillel Chapman

IPC: G06F13/16 ,  G06F13/42 ,  G06F13/38 ,  G06F12/02 ,  G06F12/0811 ,  G06F15/78

Abstract: A system and method are provided. In one example, a system is disclosed that includes a memory device and a first interface configured to connect with a first external device. The interface may include a device side that enables a first data exchange with the first external device and a system side that enables a second data exchange with the memory device, where the system side further enables an exchange of platform hints between the first interface and the memory device. The system may also include a hinting unit that populates the platform hints in an address bit.

公开(公告)号：US20220158772A1

公开(公告)日：2022-05-19

申请号：US17107990

申请日：2020-12-01

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Roee Moyal ,  Ariel Shahar ,  Noam Bloch ,  Ran Koren

IPC: H04L1/18 ,  G06F15/173

Abstract: A method for data transfer includes transmitting a sequence of data packets from a first computer over a network to a second computer in a single RDMA data transfer transaction. Upon receipt of a second packet in the sequence without previously having received the first packet, the second computer sends a NAK packet over the network to the first computer, indicating that the first packet was not received. A retransmission mode is selected responsively to the type of the transaction, such that when the transaction is of a first type, the first packet is retransmitted from the first computer to the second computer in response to the NAK packet without retransmitting the second packet, and when the transaction is of a second type, both the first and second packets are retransmitted from the first computer to the second computer in response to the NAK packet.

公开(公告)号：US20220129395A1

公开(公告)日：2022-04-28

申请号：US17079536

申请日：2020-10-26

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Eliav Bar-Ilan ,  Oren Duer ,  Amir Ancel ,  Yossi Kendel ,  Idan Burstein

IPC: G06F13/16 ,  G06F12/123

Abstract: In one embodiment, data communication apparatus includes a network interface including one or more ports for connection to a packet data network and configured to receive content transfer requests from at least one remote device over the network, a storage sub-system to be connected to local peripheral storage devices, and including at least one peripheral interface, and a memory sub-system including a cache and RAM, and processing circuitry to manage transfer of content between the remote device(s) and the local peripheral storage devices via the peripheral interface(s) and the cache, responsively to the content transfer requests, while pacing commencement of serving of respective ones of the content transfer requests responsively to a metric of the storage sub-system so that while ones of the content transfer requests are being served, other ones of the content transfer requests pending serving are queued in at least one pending queue.

公开(公告)号：US20210111996A1

公开(公告)日：2021-04-15

申请号：US17108002

申请日：2020-12-01

Applicant: Mellanox Technologies, Ltd

Inventor： Boris Pismenny ,  Miriam Menes ,  Idan Burstein ,  Liran Liss ,  Noam Bloch ,  Ariel Shahar

IPC: H04L12/721 ,  H04L12/717 ,  H04L29/06 ,  G06F11/10

Abstract: A system includes a host processor, which has a host memory and is coupled to store data in a non-volatile memory in accordance with a storage protocol. A network interface controller (NIC) receives data packets conveyed over a packet communication network from peer computers containing, in payloads of the data packets, data records that encode data in accordance with the storage protocol for storage in the non-volatile memory. The NIC processes the data records in the data packets that are received in order in each flow from a peer computer and extracts and writes the data to the host memory, and when a data packet arrives out of order, writes the data packet to the host memory without extracting the data and processes the data packets in the flow so as to recover context information for use in processing the data records in subsequent data packets in the flow.

公开(公告)号：US10552367B2

公开(公告)日：2020-02-04

申请号：US15659876

申请日：2017-07-26

Applicant: Mellanox Technologies, Ltd.

Inventor： Idan Burstein ,  Diego Crupnicoff

IPC: G06F15/167 ,  G06F15/173 ,  H04L29/06

Abstract: Communication apparatus includes a host interface, configured to be coupled to a host processor having a host memory, and a network interface, which is configured to receive over a network from a sending node data packets conveying operations for execution in a sequential order on a predefined queue pair (QP), including at least a first packet conveying a posted write operation and a second packet conveying a non-posted write operation. Packet processing circuitry is configured to execute the posted write operation in accordance with the sequential order so as to write first data to the host memory prior to the execution of any subsequent operations in the sequential order, and to execute the non-posted write operation so as to write second data to the host memory while allowing one or more of the subsequent operations in the sequential order to be executed prior to completion of writing the second data.

公开(公告)号：US10516710B2

公开(公告)日：2019-12-24

申请号：US15473668

申请日：2017-03-30

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan Levi ,  Idan Burstein ,  Shlomi Museri ,  Richard Hastie

IPC: G06F15/16 ,  H04L29/06 ,  H04L12/861 ,  H04L12/707 ,  H04L12/801

Abstract: Communication apparatus includes a host interface and a network interface, which receives at least first and second redundant packet streams, each including a sequence of data packets, which include headers containing respective packet sequence numbers and data payloads of a predefined, fixed size containing respective slices of the data segment. Redundant first and second copies of each slice are transmitted in respective packets in the first and second packet streams. Packet processing circuitry receives the data packets from the network interface, maps the data packets in both the first and second packet streams, using the packet sequence numbers, to respective addresses in a buffer, and writes the data payloads to the respective addresses via the host interface while eliminating redundant data so that the buffer contains exactly one copy of each slice of the data segment, ordered in accordance with the packet sequence numbers.

公开(公告)号：US10324513B2

公开(公告)日：2019-06-18

申请号：US14836988

申请日：2015-08-27

Applicant: MELLANOX TECHNOLOGIES LTD.

Inventor： Idan Burstein ,  Shlomo Raikin ,  Noam Bloch ,  Lavi Koch

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G06F1/3209 ,  G06F1/324 ,  H04L12/10

Abstract: A method for processing data includes receiving in a peripheral device, which is connected by a bus to a host processor having host resources, a notification of a sleep state of at least one of the host resources. While the at least one of the host resources is in the sleep state, when the peripheral device receives data from a data source for delivery to the host processor, the peripheral device sends a message to the data source, which causes the data source to defer conveying further data to the peripheral device until the at least one of the host resources has awakened from the sleep state.

公开(公告)号：US10110518B2

公开(公告)日：2018-10-23

申请号：US14132014

申请日：2013-12-18

Applicant: Mellanox Technologies Ltd.

Inventor： Idan Burstein ,  Michael Kagan ,  Noam Bloch ,  Ariel Shachar ,  Hillel Chapman ,  Dror Bohrer ,  Diego Crupnicoff

IPC: H04L12/861 ,  H04L12/879 ,  H04L29/08 ,  G06F15/173

Abstract: A method for communication includes receiving at a receiving node over a network from a sending node a succession of data packets belonging to a sequence of transactions, including at least one or more first packets belonging to a first transaction and one or more second packets belonging to a second transaction executed by the sending node after the first transaction, wherein at least one of the second packets is received at the receiving node before at least one of the first packets. At the receiving node, upon receipt of the data packets, data are written from the data packets in the succession to respective locations in a buffer. Execution of the second transaction at the receiving node is delayed until all of the first packets have been received and the first transaction has been executed at the receiving node.

公开(公告)号：US20160294715A1

公开(公告)日：2016-10-06

申请号：US14673892

申请日：2015-03-31

Applicant: Mellanox Technologies Ltd.

Inventor： Shachar Raindel ,  Idan Burstein ,  Noam Bloch ,  Benny Koren ,  Barak Gafni ,  Dror Goldenberg ,  Liran Liss

IPC: H04L12/801 ,  H04L12/721 ,  H04L12/803 ,  H04L12/707

CPC classification number: H04L47/34 ,  H04L45/22 ,  H04L45/38 ,  H04L47/122

Abstract: A method in a network element that includes multiple interfaces for connecting to a communication network includes receiving from the communication network via an ingress interface a flow including a sequence of packets, and routing the packets to a destination of the flow via a first egress interface. A permission indication for re-routing the flow is received in the ingress interface. In response to receiving the permission indication, subsequent packets of the flow are re-routed via a second egress interface that is different from the first egress interface. Further re-routing of the flow is refrained from, until receiving another permission indication.

Abstract translation: 包括用于连接到通信网络的多个接口的网络元件中的方法包括经由入口接口从通信网络接收包括一系列分组的流，以及经由第一出口接口将分组路由到流的目的地。 在入口接口中接收到重新路由流量的许可指示。 响应于接收到许可指示，流的后续分组经由与第一出口接口不同的第二出口接口重新路由。 直到收到另一个许可指示为止，进一步重新路由流。