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公开(公告)号：US20230260581A1
公开(公告)日：2023-08-17
申请号：US17651218
申请日：2022-02-15
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer , Innocenzo Tortorelli
CPC classification number: G11C16/34 , G11C16/102 , G11C16/26 , G11C16/0433 , G11C16/08 , G11C16/24
Abstract: Methods, systems, and devices for techniques for operating a vertical memory architecture are described. A memory device may include memory cells arranged in a three-dimensional vertical memory architecture. Each memory cell may include a storage element (e.g., a chalcogenide material), where a logic state may be programmed at the storage element based on a polarity of an applied voltage that exceeds a threshold voltage. The storage element may be coupled with a selection element and a conductive line. The selection element may be coupled with a bit line decoder and a word line decoder via vertical pillars. The selection element may selectively couple the storage element with the bit line decoder. In some examples, an activation voltage for the selection element may be less than a threshold voltage of the storage element.
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公开(公告)号：US11721394B2
公开(公告)日：2023-08-08
申请号：US17511484
申请日：2021-10-26
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
CPC classification number: G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/004 , G11C2013/005 , G11C2013/0073
Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.
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公开(公告)号：US20230005535A1
公开(公告)日：2023-01-05
申请号：US17864015
申请日：2022-07-13
Applicant: Micron Technology, Inc.
Inventor： Lorenzo Fratin , Fabio Pellizzer , Agostino Pirovano , Russell L. Meyer
IPC: G11C13/00 , H01L23/528
Abstract: Methods, systems, and devices for self-selecting memory with horizontal access lines are described. A memory array may include first and second access lines extending in different directions. For example, a first access line may extend in a first direction, and a second access line may extend in a second direction. At each intersection, a plurality of memory cells may exist, and each plurality of memory cells may be in contact with a self-selecting material. Further, a dielectric material may be positioned between a first plurality of memory cells and a second plurality of memory cells in at least one direction. each cell group (e.g., a first and second plurality of memory cells) may be in contact with one of the first access lines and second access lines, respectively.
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公开(公告)号：US20220036946A1
公开(公告)日：2022-02-03
申请号：US17399853
申请日：2021-08-11
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices related to a multi-level self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more durations during which a fixed level of voltage or fixed level of current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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公开(公告)号：US20220013167A1
公开(公告)日：2022-01-13
申请号：US16926557
申请日：2020-07-10
Applicant: Micron Technology, Inc.
Inventor： Mattia Robustelli , Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano
Abstract: Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.
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Patent Agency Ranking
公开(公告)号：US11164627B2
公开(公告)日：2021-11-02
申请号：US16257521
申请日：2019-01-25
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.
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公开(公告)号：US11024372B2
公开(公告)日：2021-06-01
申请号：US16102493
申请日：2018-08-13
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Agostino Pirovano , Innocenzo Tortorelli
IPC: G11C13/00
Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.
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公开(公告)号：US10896932B2
公开(公告)日：2021-01-19
申请号：US16513797
申请日：2019-07-17
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Innocenzo Tortorelli , Agostino Pirovano , Andrea Redaelli
Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.
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公开(公告)号：US20200303640A1
公开(公告)日：2020-09-24
申请号：US16877154
申请日：2020-05-18
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Anna Maria Conti , Agostino Pirovano
Abstract: Methods, systems, and devices for a tapered cell profile and fabrication are described. A memory storage component may contain multiple chalcogenide materials and may include a tapered profile. For example, a first chalcogenide material may be coupled with a second chalcogenide material. Each of the chalcogenide materials may be further coupled with a conductive material (e.g., an electrode). Through an etching process, the chalcogenide materials may tapered (e.g., step tapered). A pulse may be applied to the tapered chalcogenide materials resulting in a memory storage component that includes a mixture of the chalcogenide materials.
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公开(公告)号：US10693066B2
公开(公告)日：2020-06-23
申请号：US16429959
申请日：2019-06-03
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Umberto M. Meotto
Abstract: Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device.
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