中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

111 records (took 0.032 seconds)

    Prefetch signaling in memory system or sub system
    71.
    发明授权
    Prefetch signaling in memory system or sub system 有权

    公开(公告)号：US11003388B2

    公开(公告)日：2021-05-11

    申请号：US16116533

    申请日：2018-08-29

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.

    Memory system and operations of the same
    72.
    发明授权
    Memory system and operations of the same 有权

    公开(公告)号：US10963168B2

    公开(公告)日：2021-03-30

    申请号：US16248685

    申请日：2019-01-15

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans

    IPC: G06F3/06 ,  G06F12/0802

    Abstract: Methods, systems, and devices related to a memory system or scheme that includes a first memory device configured for low-energy access operations and a second memory device configured for storing high-density information and operations of the same are described. The memory system may include an array configured for high-density information and may interface with a host via a controller and a cache or another array of a relatively fast memory type. The memory system may support signals communicated according to one or several modulation schemes, including a modulation scheme or schemes that employ two, three, or more voltage levels (e.g., NRZ, PAM4). The memory system may include, e.g., separate channels configured to communicate using different modulation schemes between a host and between memory arrays or memory types within the memory system.

    Prefetching data based on data transfer within a memory system
    73.
    发明授权
    Prefetching data based on data transfer within a memory system 有权

    公开(公告)号：US10956333B2

    公开(公告)日：2021-03-23

    申请号：US16105545

    申请日：2018-08-20

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F12/0862 ,  G06F13/20

    Abstract: Methods, systems, and devices are described for wireless communications. A request for data located in a memory page of a memory array may be received at a device, and a value of a prefetch counter associated with the memory page may be identified. A portion of the memory page that includes the requested data may then be communicated between a memory array and memory bank of the device based on the value of the prefetch counter. For instance, the portion of the memory page may be selected based on the value of the prefetch counter. A second portion of the memory page may be communicated to a buffer of the device, and the value of the prefetch counter may be modified based on a relationship between the first portion of the memory page and the second portion of the memory page.

    Apparatuses and methods for configurable memory array bank architectures
    74.
    发明授权
    Apparatuses and methods for configurable memory array bank architectures 有权

    公开(公告)号：US10788985B2

    公开(公告)日：2020-09-29

    申请号：US16452424

    申请日：2019-06-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Dean D. Gans ,  Shunichi Saito

    IPC: G06F3/06 ,  G06F12/10

    Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

    Memory buffer management and bypass
    75.
    发明授权
    Memory buffer management and bypass 有权

    公开(公告)号：US10754578B2

    公开(公告)日：2020-08-25

    申请号：US15975607

    申请日：2018-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Dean D. Gans ,  Sharookh Daruwalla

    IPC: G06F3/06 ,  G06F13/16 ,  G06F12/1009 ,  G06F12/02

    Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.

    MEMORY WITH VIRTUAL PAGE SIZE
    80.
    发明申请
    MEMORY WITH VIRTUAL PAGE SIZE 审中-公开

    公开(公告)号：US20190065105A1

    公开(公告)日：2019-02-28

    申请号：US15684773

    申请日：2017-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Dean D. Gans

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: Methods, systems, and devices for memory with a virtual page size are described. Memory cells may be accessed in portions or page sizes that are tailored to a particular use or application. A variable page size may be defined that represents a subset or superset of memory cells in a nominal page size for the array. For example, memory cells associated with a page size of a memory array may be accessed with commands to a memory array. Each command may contain a particular addressing scheme based on the page size of the memory array and may activate one or more sets of memory cells within the array. The addressing scheme may be modified based on the page size of the memory array. Upon activating a desired set of memory cells, one or more individual activated cells may be accessed.

Patent Agency Ranking