公开(公告)号：US11289146B2

公开(公告)日：2022-03-29

申请号：US16552984

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.

公开(公告)号：US20220068335A1

公开(公告)日：2022-03-03

申请号：US17498919

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto di Vincenzo

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C16/34

Abstract: A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.

公开(公告)号：US11164626B2

公开(公告)日：2021-11-02

申请号：US16771657

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/00 ,  G11C13/00

Abstract: A method for reading memory cell, comprising the steps of applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, based on the first threshold voltages, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, wherein the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, based on the second threshold voltages, associating a second logic state to one or more cells of the plurality of memory cells, applying a third read voltage to the plurality of memory cells, wherein the third read voltage has the same polarity of the first and second read voltages and is applied at least to a group of memory cells that, during the application the second read voltage, have been reprogrammed to an opposite logic state, detecting third threshold voltages exhibited by the plurality of memory cells in response to application of the third read voltage, and based on the third threshold voltages, associating one of the first or second logic state to one or more of the cells of the of the plurality of memory cells. A related circuit, a related memory device and a related system are also disclosed.

公开(公告)号：US11152049B1

公开(公告)日：2021-10-19

申请号：US16895956

申请日：2020-06-08

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and devices for differential sensing for a memory device are described. A memory device in accordance with examples as disclosed herein may include a sense component having a signal development component for generating a sense signal, a reference component for generating a reference signal, and a tail component coupled with the signal development component and the reference component. The tail component may be configured for canceling common aspects of the sense signal and the reference signal. Additionally or alternatively, a memory device in accordance with examples as disclosed herein may include a sense component having a sense amplifier configured to operate in multiple power domains, with one power domain associated with sense signal and reference signal generation and comparison, and another power domain associated with logical signal or information transfer.

公开(公告)号：US11062763B2

公开(公告)日：2021-07-13

申请号：US16379222

申请日：2019-04-09

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Stefan Frederik Schippers

IPC: G11C11/24 ,  G11C11/4096 ,  G11C11/4091 ,  G11C11/408 ,  H01L27/108 ,  G11C11/56

Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

公开(公告)号：US10978128B2

公开(公告)日：2021-04-13

申请号：US16586334

申请日：2019-09-27

Applicant: Micron Technology, Inc.

Inventor： Alessandro Calderoni ,  Durai Vishak Nirmal Ramaswamy ,  Kirk Prall ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C29/52 ,  G06F11/10

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A cell may be written with a value that is intended to convey a different logic state than may typically be associated with the value. For example, a cell that has stored a charge associated with one logic state for a time period may be re-written to store a different charge, and the re-written cell may still be read to have the originally stored logic state. An indicator may be stored in a latch to indicate whether the logic state currently stored by the cell is the intended logic state of the cell. A cell may, for example, be re-written with an opposite value periodically, based on the occurrence of an event, or based on a determination that the cell has stored one value (or charge) for a certain time period.

公开(公告)号：US10916288B1

公开(公告)日：2021-02-09

申请号：US16515666

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C7/00 ,  G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

公开(公告)号：US20210020221A1

公开(公告)日：2021-01-21

申请号：US16515666

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

公开(公告)号：US20200372943A1

公开(公告)日：2020-11-26

申请号：US16523404

申请日：2019-07-26

Applicant: Micron Technology, Inc

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

公开(公告)号：US20200321053A1

公开(公告)日：2020-10-08

申请号：US16905104

申请日：2020-06-18

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto Di Vincenzo

IPC: G11C13/00 ,  G11C16/28 ,  G11C7/10 ,  G11C16/04

Abstract: Methods, systems, devices, and techniques for read operations are described. In some examples, a memory device may include a first transistor (e.g., memory node transistor) configured to receive a precharge voltage at a first gate and output first voltage based on a threshold of the first transistor to a reference node via a first switch. The device may include a second transistor (e.g., a reference node transistor) configured to receive a precharge voltage and output a second voltage based on a threshold of the second transistor to a memory node via a second switch. The first voltage may be modified by a reference voltage and input to the second transistor. The second voltage may be modified by a voltage stored on a memory cell and input to the first transistor. The first and second transistor may output third and fourth voltages to be sampled to a latch.