公开(公告)号：US11657866B2

公开(公告)日：2023-05-23

申请号：US17459722

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder

IPC: G11C7/22 ,  G11C11/4076 ,  G06F1/3234 ,  H03L7/081 ,  G11C11/4096 ,  G11C11/4093 ,  G06F1/3296

CPC classification number: G11C11/4076 ,  G06F1/3275 ,  G06F1/3296 ,  G11C11/4093 ,  G11C11/4096 ,  H03L7/0814 ,  G11C7/222

Abstract: A memory device includes a command interface configured to receive a command from a host device. The memory device also includes a command shifter configured to receive the command. The command shifter includes a plurality of stages coupled in series and configured to delay the command. The command shifter comprises selection circuitry configured to receive the command and to select an insertion stage of the plurality of stages for the command. The selection circuitry is configured to select the insertion stage as a location to insert the command. The selected insertion stage is selected to control a duration of delay in the command shifter. The selection of the insertion stage is based at least in part on a path delay between a clock and a data pin of the memory device.

公开(公告)号：US20230007872A1

公开(公告)日：2023-01-12

申请号：US17369055

申请日：2021-07-07

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Navya Sri Sreeram ,  William C. Waldrop ,  Vijayakrishna J. Vankayala

IPC: G11C11/4076 ,  G11C11/4096 ,  G06F3/06

Abstract: Methods of operating a memory device are disclosed. A method may include asserting, at a semiconductor device, an internal signal in response to receipt of a command. The method may also include holding the internal signal in an asserted state for at least a predetermined time duration upon assertion of the internal signal. Further, the method may include generating an enable signal based on the internal signal and a clock signal. Associated devices and systems are also disclosed.

公开(公告)号：US11232830B1

公开(公告)日：2022-01-25

申请号：US17119226

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Harish V. Gadamsetty

IPC: G11C7/00 ,  G11C11/4091 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093

Abstract: Devices and methods include a command interface configured to receive commands, such as a write with an automatic precharge. A bank-specific decoder decodes the write with an automatic precharge command for a corresponding memory bank and outputs a write auto-precharge (WrAP) signal. This WrAP signal has not been adjusted for a write recovery time for the memory bank. Accordingly, bank processing circuitry in a bank receiving the WrAP signal uses the WrAP to cause its internal lockout circuitry to apply a tWR lockout based at least in part on a mode register setting and on the WrAP signal indicating receipt of the write with an automatic precharge command.

公开(公告)号：US11217295B2

公开(公告)日：2022-01-04

申请号：US16600355

申请日：2019-10-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Jason M. Brown ,  Derek R. May ,  Jeffrey E. Koelling ,  Roger D. Norwood

IPC: G11C11/406 ,  G11C11/408 ,  G06F11/34

Abstract: Apparatuses and methods for address detection are disclosed herein. An example apparatus it an address filter and an address tracking circuit. The address filter may be configured to receive a first address and to determine whether the first address matches an address of a plurality of addresses associated with the address filter. The address tracking circuit may be coupled to the address filter and configured to store the first address responsive to a determination that the first address matches an address of the plurality of addresses associated with the address filter. The address tracking circuit may further be configured to receive a second address and to change a count associated with the first address based on the second address matching the first address. The address tracking circuit may be configured to selectively provide the first address responsive to the count.

公开(公告)号：US11056171B1

公开(公告)日：2021-07-06

申请号：US16737727

申请日：2020-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Kangjoo Lee ,  Ming-Bo Liu

IPC: G11C11/407 ,  G11C11/409 ,  G11C11/4076 ,  G11C11/4093

Abstract: Apparatuses and methods for wide clock frequency range command paths are disclosed. An example apparatus includes a command decoder and a command timing circuit. The command decoder is configured to receive a command and is further configured to decode the command to provide a decoded command. The command timing circuit is configured to receive the decoded command responsive to a clock and is further configured to provide a delayed internal command having a delay relative to receiving the decoded command based on clock frequency information indicative of a clock frequency of the clock. The command timing circuit includes a plurality of command timing paths. Each of the plurality of command timing paths is configured to provide a respective delay to the decoded command for a respective range of clock frequencies.

公开(公告)号：US20210201978A1

公开(公告)日：2021-07-01

申请号：US16737727

申请日：2020-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Kangjoo Lee ,  Ming-Bo Liu

IPC: G11C11/4076 ,  G11C11/4093

Abstract: Apparatuses and methods for wide clock frequency range command paths are disclosed. An example apparatus includes a command decoder and a command timing circuit. The command decoder is configured to receive a command and is further configured to decode the command to provide a decoded command. The command timing circuit is configured to receive the decoded command responsive to a clock and is further configured to provide a delayed internal command having a delay relative to receiving the decoded command based on clock frequency information indicative of a clock frequency of the clock. The command timing circuit includes a plurality of command timing paths. Each of the plurality of command timing paths is configured to provide a respective delay to the decoded command for a respective range of clock frequencies.

公开(公告)号：US10606512B2

公开(公告)日：2020-03-31

申请号：US15790896

申请日：2017-10-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Myung-Ho Bae

IPC: G06F3/00 ,  G06F3/06 ,  G11C29/02 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/419

Abstract: Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.

公开(公告)号：US20200073775A1

公开(公告)日：2020-03-05

申请号：US16678691

申请日：2019-11-08

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  William O'Leary

IPC: G06F11/267 ,  G11C7/10 ,  G11C29/00 ,  G11C29/16 ,  G11C8/08 ,  G11C7/22 ,  G11C8/10 ,  H03K19/173

Abstract: Apparatuses and methods for nested mode registers to extend mode register functionality are disclosed. An example apparatus comprises a mode register configured to store address information and write data, a plurality of nested mode registers coupled to the mode register and configured to store the write data, and a decoder circuit coupled to the mode register and the plurality of nested mode registers and configured to selectively enable a nested mode register of the plurality of nested mode registers to store the write data based, at least in part, on the address information.

公开(公告)号：US20190287581A1

公开(公告)日：2019-09-19

申请号：US16428741

申请日：2019-05-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder

IPC: G11C7/10 ,  G11C29/02 ,  H03K19/0175 ,  H03K19/003 ,  G11C7/22 ,  G11C29/50 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4063

Abstract: Devices, systems, and methods include controls for on-die termination (ODT) and data strobe signals. For example, a command to de-assert ODT for a data pin (DQ) during the read operation. An input, such as a mode register, receives an indication of a shift mode register value that corresponds to a number of shifts of a rising edge of the command in a backward or a falling edge in a forward direction. A delay chain delays the appropriate edge of received command the number of shifts in the corresponding direction to generate a shifted edge command signal. Combination circuitry then combines a falling edge command signal with a shifted rising edge command signal to form a transformed command.

公开(公告)号：US20190121577A1

公开(公告)日：2019-04-25

申请号：US15790896

申请日：2017-10-23

Applicant: Micron Technology, Inc.

Inventor： Kallol Mazumder ,  Myung-Ho Bae

IPC: G06F3/06

Abstract: Methods and devices that receive commands at a command interface and uses control circuitry configured to implement the command. A routing pipeline is configured to translate and route the command from the command interface to the control circuitry. The routing pipeline includes clock circuitry. The clock circuitry includes a clock delay line and multiple cloned delay lines derived from the clock delay line. Each of the cloned delay lines are dedicated to a command type of multiple command types. The routing pipeline also includes delay circuitry configured to utilize the cloned delay lines to shift a data pin signal of the semiconductor device or shift a data strobe pin signal of the semiconductor device.