中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

283 records (took 0.021 seconds)

    MEMORY DEVICE HAVING SHARED READ/WRITE ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL
    71.
    发明申请
    MEMORY DEVICE HAVING SHARED READ/WRITE ACCESS LINE FOR 2-TRANSISTOR VERTICAL MEMORY CELL 有权

    公开(公告)号：US20220392511A1

    公开(公告)日：2022-12-08

    申请号：US17887903

    申请日：2022-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Karthik Sarpatwari ,  Kamal M. Karda ,  Durai Vishak Nirmal Ramaswamy

    IPC: G11C11/402 ,  H01L27/105 ,  G11C11/409 ,  H01L29/78 ,  H01L29/22

    Abstract: Some embodiments include apparatuses and methods operating the apparatuses. One of the apparatuses includes a first data line located over a substrate, a second data line located over the first data line, a third data line located over the second data line and electrically separated from the first and second data lines, and a memory cell coupled to the first, second, and third data lines. The memory cell includes a first material between the first and second data lines and electrically coupled to the first and second data lines; a second material located over the first data line and the first material, the second material electrically separated from the first material and electrically coupled to the third data line; and a memory element electrically coupled to the second material and electrically separated from the first material and first and second data lines.

    SELF-ALIGNED ETCH BACK FOR VERTICAL THREE DIMENSIONAL (3D) MEMORY
    72.
    发明申请
    SELF-ALIGNED ETCH BACK FOR VERTICAL THREE DIMENSIONAL (3D) MEMORY 有权

    公开(公告)号：US20220344338A1

    公开(公告)日：2022-10-27

    申请号：US17237664

    申请日：2021-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Litao Yang ,  Si-Woo Lee ,  Haitao Liu ,  Kamal M. Karda

    IPC: H01L27/108 ,  H01L27/11507 ,  H01L27/11514

    Abstract: Systems, methods, and apparatuses are provided for self-aligned etch back for vertical three dimensional (3D) memory. One example method includes depositing layers of a first dielectric material, a semiconductor material, and a second dielectric material to form a vertical stack, forming first vertical openings to form elongated vertical, pillar columns with first vertical sidewalls in the vertical stack, and forming second vertical openings through the vertical stack to expose second vertical sidewalls. Further, the example method includes removing portions of the semiconductor material to form first horizontal openings and depositing a fill in the first horizontal openings. The method can further include forming third vertical openings to expose third vertical sidewalls in the vertical stack and selectively removing the fill material to form a plurality of second horizontal openings in which to form horizontally oriented storage nodes.

    Memory device having 2-transistor memory cell and access line plate
    74.
    发明授权
    Memory device having 2-transistor memory cell and access line plate 有权

    公开(公告)号：US11335684B2

    公开(公告)日：2022-05-17

    申请号：US17003077

    申请日：2020-08-26

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Karthik Sarpatwari ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L27/00 ,  H01L29/00 ,  H01L27/105 ,  H01L27/12 ,  H01L29/788 ,  H01L29/24 ,  H01L29/786

    Abstract: Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

    Ferroelectric Transistors and Assemblies Comprising Ferroelectric Transistors
    80.
    发明申请
    Ferroelectric Transistors and Assemblies Comprising Ferroelectric Transistors 有权

    公开(公告)号：US20210066502A1

    公开(公告)日：2021-03-04

    申请号：US16983841

    申请日：2020-08-03

    Applicant: Micron Technology, Inc.

    Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L29/78 ,  H01L29/51

    Abstract: Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by an active region. A transistor gate is along a portion of the active region. The active region includes a first source/drain region adjacent the first electrode, a second source/drain region adjacent the second electrode, and a body region between the first and second source/drain regions. The body region includes a gated channel region adjacent the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region which is permeable to electrons but not to holes. Ferroelectric material is between the transistor gate and the gated channel region.

Patent Agency Ranking