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公开(公告)号：US11276468B2
公开(公告)日：2022-03-15
申请号：US16944568
申请日：2020-07-31
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G11C16/26 , G11C16/12 , H03K19/017 , H03K19/0185 , G11C16/04
Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.
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公开(公告)号：US20200273535A1
公开(公告)日：2020-08-27
申请号：US16811717
申请日：2020-03-06
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: G11C29/00
Abstract: A memory device includes a memory bank accessible via a plurality of memory addresses. The memory device further includes a fuse array including a plurality of fuse banks. A fuse bank of the plurality of fuse banks includes a fuse circuit, which includes a fuse latch having first input circuitry. The fuse latch is implemented to store a first bit of a first memory address received at the first input circuitry. The fuse circuit also includes a matching circuit coupled to the first input circuitry. The matching circuit is implemented to receive a first bit of a second memory address at the first input circuitry and to output, at output circuitry, a comparison result based at least in part on the first bit of the first memory address and the first bit of the second memory address.
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公开(公告)号：US10381103B2
公开(公告)日：2019-08-13
申请号：US15681183
申请日：2017-08-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Christopher Morzano , Sujeet Ayyapureddi
IPC: G11C29/00
Abstract: Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.
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公开(公告)号：US20190057758A1
公开(公告)日：2019-02-21
申请号：US15681183
申请日：2017-08-18
Applicant: Micron Technology, Inc.
Inventor： Christopher Morzano , Sujeet Ayyapureddi
IPC: G11C29/00
CPC classification number: G11C29/765 , G11C29/72 , G11C29/785
Abstract: Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.
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公开(公告)号：US20150023386A1
公开(公告)日：2015-01-22
申请号：US14507511
申请日：2014-10-06
Applicant: Micron Technology, Inc.
Inventor： Manoj Sinha , Sujeet Ayyapureddi , Brandon Roth
CPC classification number: G01K15/005 , G01K7/015 , G01K7/16 , G01K15/00
Abstract: There is provided a system and method for automatically calibrating a temperature sensor. More specifically, there is provided a system including a temperature sensor that includes a first resistance configured to indicate a temperature of the temperature sensor and a second resistance, in series with the first resistor, wherein the second resistance is adjustable to calibrate the first resistance, and a calibration circuit, coupled to the temperature sensor and configured to automatically calibrate the first resistance.
Abstract translation: 提供了一种用于自动校准温度传感器的系统和方法。 更具体地，提供了一种系统，包括温度传感器，其包括被配置为指示温度传感器的温度的第一电阻和与第一电阻器串联的第二电阻，其中第二电阻可调整以校准第一电阻， 以及校准电路，其耦合到所述温度传感器并且被配置为自动校准所述第一电阻。
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Patent Agency Ranking
公开(公告)号：US20140040922A1
公开(公告)日：2014-02-06
申请号：US14046738
申请日：2013-10-04
Applicant: Micron Technology, Inc.
IPC: G06F9/44
CPC classification number: G06F9/4411 , G11C7/04 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C2207/2254
Abstract: Driver systems and methods are provided, such as those that include identifying a process corner of a driver; and configuring the driver based on the identified process corner. Further embodiments provide a method that includes detecting a process corner of a driver, setting a reference voltage of a calibration circuit based on the process corner detected, and configuring the driver based on the reference voltage.
Abstract translation: 提供了驱动器系统和方法，例如包括识别驾驶员的过程角的那些; 并基于识别的过程角来配置驱动程序。 另外的实施例提供了一种方法，其包括检测驾驶员的过程角，基于检测到的过程角度来设置校准电路的参考电压，以及基于参考电压配置驾驶员。
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公开(公告)号：US20250078949A1
公开(公告)日：2025-03-06
申请号：US18745577
申请日：2024-06-17
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sujeet Ayyapureddi
IPC: G11C29/52 , G11C11/408 , G11C11/4096
Abstract: Apparatuses, systems, and methods for half-page modes. A memory device may be operated in a full-page mode where all the memory cells along a word line are used for data or a half-page mode where less than all of the memory cells are used for data. In some memory devices, each half of the memory cells may be separately activated by different word line portions. In some half-page modes, data may be stored along a selected portion of the memory cells and additional information such as metadata or module parity may be stored along the non-selected portion of the memory cells. The additional information may be provided along additional data terminals so as not to increase the data burst length.
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公开(公告)号：US20250031136A1
公开(公告)日：2025-01-23
申请号：US18767700
申请日：2024-07-09
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
IPC: H04W48/16 , G08G1/0967 , H04W4/40 , H04W52/38 , H04W84/18
Abstract: Systems and methods determining a range for seeking data sources for a dynamic ad hoc network of a vehicle are disclosed including receiving information about the vehicle, determining a range for seeking data sources of the dynamic ad hoc network for the vehicle based on the received information, receiving navigation or safety information from one or more other vehicles in the dynamic ad hoc network, and determining one or more control inputs to the vehicle based at least in part on the received navigation or safety information from one or more other vehicles in the dynamic ad hoc network.
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公开(公告)号：US20250031020A1
公开(公告)日：2025-01-23
申请号：US18767664
申请日：2024-07-09
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
Abstract: Systems and methods for sharing intermediate classifications in a dynamic ad hoc network are disclosed including determining, using a machine learning model executed by a vehicle control circuit and information from one or more sensors of the vehicle, one or more intermediate classifications and respective confidence indications for the one or more determined intermediate classifications, determining a first identification with a first confidence indication using at least one of the one or more determined intermediate classifications, receiving one or more intermediate classifications from the dynamic ad hoc network, and determining a composite identification as a function of the one or more received intermediate classifications from the dynamic ad hoc network and at least one of the one or more determined intermediate classifications by the vehicle control circuit or the determined first identification by the vehicle control circuit.
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公开(公告)号：US20250031012A1
公开(公告)日：2025-01-23
申请号：US18767587
申请日：2024-07-09
Applicant: Micron Technology, Inc.
Inventor： Sujeet Ayyapureddi
Abstract: Systems and methods for adjusting a dynamic ad hoc network of a vehicle are disclosed including determining a classification and a confidence indication for the determined classification using information from at least one sensor of the vehicle, determining a size of the dynamic ad hoc network for the vehicle based on the determined confidence indication, receiving navigation or safety information from one or more other vehicles in the dynamic ad hoc network, and determining one or more additional control inputs to the vehicle based at least in part on the received navigation or safety information from one or more other vehicles in the dynamic ad hoc network.
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