公开(公告)号：US20120324264A1

公开(公告)日：2012-12-20

申请号：US13593717

申请日：2012-08-24

申请人： Heather L. Hanson ,  Charles R. Lefurgy ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

发明人： Heather L. Hanson ,  Charles R. Lefurgy ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

IPC分类号： G06F1/26

CPC分类号： G06F9/5061 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/36

摘要： A mechanism is provided for priority-based power capping. A power management controller identifies a set of priorities for a set of partitions of the data processing system. The power management controller determines whether a measured power of the data processing system exceeds a power cap for the data processing system. Responsive to the measured power exceeding the power cap, the power management controller sends a set of commands to a set of component actuators to adjust one or more of a set of operation parameters for a set of components associated with the set of partitions using the set of priorities. The set of component actuators adjust the one or more of the set of operational parameters associated with the set of component in order to reduce a power consumption of the data processing system.

公开(公告)号：US08261112B2

公开(公告)日：2012-09-04

申请号：US12330284

申请日：2008-12-08

申请人： John B. Carter ,  Heather L. Hanson ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

发明人： John B. Carter ,  Heather L. Hanson ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Malcolm S. Ware

IPC分类号： G06F1/32 ,  G06F1/26 ,  G06F1/08

CPC分类号： G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.

摘要翻译： 一种用于优化执行中的执行处理器的功耗的方法，系统和计算机程序产品。 该方法包括分别基于在第一和第二操作频率（OF）下测量的第一和第二性能量度值（PMV）来确定第一灵敏度关系（SR）。 第一个SR预测一系列OFs的工作负载性能。 基于第一个SR和指定的工作负载性能底线确定三分之一。 通过执行在第三个OF操作的处理器来测量第三个PMV。 然后确定基于第二和第三PMV的第二SR。 逻辑上组合第一和第二SR以产生第三SR。 基于第三SR，输出第四个OF。

公开(公告)号：US08140868B2

公开(公告)日：2012-03-20

申请号：US12191757

申请日：2008-08-14

申请人： Wesley Michael Felter ,  Thomas Walter Keller, Jr. ,  Karthick Rajamani ,  Cosmin Rusu

发明人： Wesley Michael Felter ,  Thomas Walter Keller, Jr. ,  Karthick Rajamani ,  Cosmin Rusu

IPC分类号： G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.

摘要翻译： 一种用于在具有多个组件的数据处理系统中管理电力的方法包括确定系统的功率预算。 然后对于每个组件预测在即将到来的时间间隔期间的活动水平。 使用预测的活动级别，在系统组件之间分配功率预算。 然后根据功率预算的相应部分为每个组件建立活动限制。 然后监视组件的活动，如果组件的活动超过组件的相应活动限制，则会受到限制。 确定预测的活动水平可以包括确定由处理器组件分派的指令的预测数量或为系统存储器组件服务的预测数量的存储器请求。 分配功率预算包括基于预期的活动水平来分配每个组件其相应的待机功率和可用于动态供电的系统功率的份额。

公开(公告)号：US20110296118A1

公开(公告)日：2011-12-01

申请号：US12789641

申请日：2010-05-28

申请人： John B. Carter ,  Karthick Rajamani

发明人： John B. Carter ,  Karthick Rajamani

IPC分类号： G06F12/00

CPC分类号： G06F13/1678

摘要： A mechanism is provided for dynamic row-width memory. The memory adapts row width to usage based on memory controller and memory management system software control. The mechanism uses an organization and control of memory array access logic. The memory controller may receive an explicit command using existing column address lines or using a command line into the memory controller. In a first option, the memory controller receives a row width and disables the unused columns and turns off the unused sense amps. In a second option, the memory controller receives a row width and adjusts row count, keeping the number of active cells constant. In a third option, the memory controller receives a row width and adjusts a number of banks.

摘要翻译： 为动态行宽存储器提供了一种机制。 存储器根据存储器控制器和存储器管理系统软件控制来适应行宽使用。 该机制使用组织和控制存储器阵列访问逻辑。 存储器控制器可以使用现有列地址线或使用命令行来接收显式命令到存储器控制器中。 在第一个选项中，存储器控制器接收行宽度并禁用未使用的列，并关闭未使用的检测放大器。 在第二个选项中，存储器控制器接收行宽并调整行数，保持活动单元的数量不变。 在第三个选项中，存储器控制器接收行宽并调整多个存储区。

公开(公告)号：US07908493B2

公开(公告)日：2011-03-15

申请号：US11758798

申请日：2007-06-06

申请人： Andreas Bieswanger ,  Michael S. Floyd ,  Soraya Ghiasi ,  Steven P. Hartman ,  Thomas W. Keller, Jr. ,  Hye-Young McCreary ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Juan C. Rubio ,  Malcolm S. Ware

发明人： Andreas Bieswanger ,  Michael S. Floyd ,  Soraya Ghiasi ,  Steven P. Hartman ,  Thomas W. Keller, Jr. ,  Hye-Young McCreary ,  Karthick Rajamani ,  Freeman L. Rawson, III ,  Juan C. Rubio ,  Malcolm S. Ware

IPC分类号： G06F1/32

CPC分类号： G06F1/206 ,  G06F1/3203

摘要： A mechanism is provided for unified management of power, performance, and thermals in computer systems. This mechanism incorporates elements to effectively address all aspects of managing computing systems in an integrated manner, instead of independently. The mechanism employs an infrastructure for real-time measurements feedback, an infrastructure for regulating system activity, component operating levels, and environmental control, a dedicated control structure for guaranteed response/preemptive action, and interaction and integration components. The mechanism provides interfaces for user-level interaction. The mechanism also employs methods to address power/thermal concerns at multiple timescales. In addition, the mechanism improves efficiency by adopting an integrated approach, rather than treating different aspects of the power/thermal problem as individual issues to be addressed in a piecemeal fashion.

摘要翻译： 提供了一种统一管理计算机系统的功率，性能和热量的机制。 该机制包含了以综合方式有效地解决管理计算系统的所有方面的元素，而不是独立的。 该机制采用基础设施进行实时测量反馈，用于调节系统活动的基础设施，组件操作级别和环境控制，用于保证响应/抢先动作的专用控制结构以及交互和集成组件。 该机制为用户级交互提供接口。 该机制还采用了多个时间尺度来解决功率/热问题的方法。 此外，该机制采用综合方法提高效率，而不是以单独的方式处理单个问题，而不是将功率/热问题的不同方面进行处理。

公开(公告)号：US20080301475A1

公开(公告)日：2008-12-04

申请号：US12191757

申请日：2008-08-14

申请人： WESLEY MICHAEL FELTER ,  Thomas Walter Keller, JR. ,  Karthick Rajamani ,  Cosmin Rusu

发明人： WESLEY MICHAEL FELTER ,  Thomas Walter Keller, JR. ,  Karthick Rajamani ,  Cosmin Rusu

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D50/20

摘要： A method for managing power in a data processing system having multiple components includes determining a power budget for the system. Activity levels during a forthcoming time interval are then predicted for each of the components. Using the predicted activity levels, the power budget is allocated among the system components. An activity limit is then established for each component based on its corresponding portion of the power budget. The activity of a component is then monitored and, if the component's activity exceeds the component's corresponding activity limit, constrained. Determining the predicted level of activity may include determining a predicted number of instructions dispatched by a processor component or a predicted number of memory requests serviced for a system memory component. Allocating the power budget includes allocating each component its corresponding standby power and a share of the system power available for dynamic powering based on the expected levels of activity.

摘要翻译： 一种用于在具有多个组件的数据处理系统中管理电力的方法包括确定系统的功率预算。 然后对于每个组件预测在即将到来的时间间隔期间的活动水平。 使用预测的活动级别，在系统组件之间分配功率预算。 然后根据功率预算的相应部分为每个组件建立活动限制。 然后监视组件的活动，如果组件的活动超过组件的相应活动限制，则会受到限制。 确定预测的活动水平可以包括确定由处理器组件分派的指令的预测数量或为系统存储器组件服务的预测数量的存储器请求。 分配功率预算包括基于预期的活动水平来分配每个组件其相应的待机功率和可用于动态供电的系统功率的份额。

公开(公告)号：US07340378B1

公开(公告)日：2008-03-04

申请号：US11565106

申请日：2006-11-30

申请人： Michael S. Floyd ,  Soraya Ghiasi ,  Thomas W. Keller, Jr. ,  Karthick Rajamani ,  Freeman Leigh Rawson, III ,  Juan C. Rubio

发明人： Michael S. Floyd ,  Soraya Ghiasi ,  Thomas W. Keller, Jr. ,  Karthick Rajamani ,  Freeman Leigh Rawson, III ,  Juan C. Rubio

IPC分类号： G06F19/00

CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

摘要翻译： 用于处理器性能测量的加权事件计数系统和方法提供低延迟和低误差性能测量能力。 加权性能计数器根据从处理器中的功能单元提供的多个事件信号累加性能计数。 根据具有处理器性能的每个事件之间的相关性，将不同的权重应用于事件信号。 权重可以由可编程寄存器提供，从而可以在程序控制下调整权重。 事件信号可以被组合以减少事件信号集合的位宽，其中在组合结果的单个字段中合并相互排斥的事件和具有根据子总计合并的相同权重的事件。 权重应用于组合结果，用于更新性能计数。 电源管理软件或硬件可以使用性能计数来对处理器的运行参数进行调整。

公开(公告)号：US08909690B2

公开(公告)日：2014-12-09

申请号：US13324025

申请日：2011-12-13

申请人： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

发明人： John B. Carter ,  Bruce G. Mealey ,  Karthick Rajamani ,  Eric E. Retter ,  Jeffrey A. Stuecheli

IPC分类号： G06F7/38

CPC分类号： G06F7/483 ,  G06F2207/382

摘要： Mechanisms are provided for performing a floating point arithmetic operation in a data processing system. A plurality of floating point operands of the floating point arithmetic operation are received and bits in a mantissa of at least one floating point operand of the plurality of floating point operands are shifted. One or more bits of the mantissa that are shifted outside a range of bits of the mantissa of at least one floating point operand are stored and a vector value is generated based on the stored one or more bits of the mantissa that are shifted outside of the range of bits of the mantissa of the at least one floating point operand. A resultant value is generated for the floating point arithmetic operation based on the vector value and the plurality of floating point operands.

摘要翻译： 提供了用于在数据处理系统中执行浮点算术运算的机构。 接收浮点算术运算的多个浮点操作数，并移位多个浮点操作数的至少一个浮点运算数的尾数中的位。 存储在至少一个浮点操作数的尾数的位的范围之外移动的尾数的一个或多个比特，并且基于所存储的一个或多个尾数位被生成向量值， 至少一个浮点操作数的尾数的位的范围。 基于向量值和多个浮点操作数，生成用于浮点运算的结果值。

公开(公告)号：US08688394B2

公开(公告)日：2014-04-01

申请号：US12878063

申请日：2010-09-09

申请人： Wael R. El-Essawy ,  Karthick Rajamani ,  Juan C. Rubio

发明人： Wael R. El-Essawy ,  Karthick Rajamani ,  Juan C. Rubio

IPC分类号： G01R21/133

CPC分类号： G05F1/66 ,  G06F1/26 ,  H04L67/12 ,  H05K7/1492 ,  H05K7/1498

摘要： A data center energy management (DCEM) server configures a power supply in the data center. The DCEM server sums input alternating current (AC) power of the power supply to a total AC power of the data center, wherein the total AC power of the data center is a sum of AC power of a plurality of power supplies. The DCEM server sums output direct current (DC) power of the power supply to a total DC power of the data center and reports a ratio of total AC power to total DC power as data center power conversion efficiency. The DCEM server sets a preset power supply efficiency threshold. The DCEM server determines that a real-time power efficiency level is below the power supply efficiency threshold. The DCEM server, responsive to a determination that real-time power efficiency level is below the power supply efficiency threshold, may remedy the power supply.

摘要翻译： 数据中心能量管理（DCEM）服务器配置数据中心的电源。 DCEM服务器将电源的输入交流电（AC）功率与数据中心的总AC电力相加，其中数据中心的总AC功率是多个电源的AC功率之和。 DCEM服务器将电源的直流输出直流功率与数据中心的总直流功率相加，并将总的交流电与总的直流功率之比报告为数据中心的电源转换效率。 DCEM服务器设置预设的电源效率阈值。 DCEM服务器确定实时功率效率水平低于电源效率阈值。 响应于确定实时功率效率水平低于电源效率阈值的DCEM服务器可以补救电源。

公开(公告)号：US08683160B2

公开(公告)日：2014-03-25

申请号：US13165982

申请日：2011-06-22

申请人： Guy L. Guthrie ,  Karthick Rajamani ,  Gregory S. Still ,  Jeffrey A. Stuecheli ,  Malcolm S. Ware

发明人： Guy L. Guthrie ,  Karthick Rajamani ,  Gregory S. Still ,  Jeffrey A. Stuecheli ,  Malcolm S. Ware

IPC分类号： G06F12/00

CPC分类号： G06Q50/10 ,  G06F12/0897

摘要： An apparatus for providing memory energy accounting within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory throttle counter, and a memory credit accounting module. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet.

摘要翻译： 公开了一种用于在具有多个小灯的数据处理系统内提供存储器能量记帐的装置。 该装置包括系统存储器，存储器访问收集模块，存储器调节计数器和存储器信用计费模块。 存储器访问收集模块从小数点内的第一高速缓冲存储器接收来自第一高速缓冲存储器的第一组信号和来自第二高速缓冲存储器的第二组信号。 存储器信用计费模块根据从小巧的第一和第二高速缓冲存储器的第一和第二组信号提取的高速缓存访​​问的结果跟踪每个用户的系统存储器的使用情况。