公开(公告)号：US20050213061A1

公开(公告)日：2005-09-29

申请号：US10808740

申请日：2004-03-25

申请人： Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： G03B27/52 ,  G03F7/20

CPC分类号： G03F7/70808 ,  G03F7/70341

摘要： A photolithographic apparatus, system and method employing an improved refractive medium. The photolithographic apparatus may be used in an immersion lithography system for projecting light onto a workpiece such as a semiconductor wafer. In one embodiment, the photolithographic apparatus includes a container containing a transparent fluid. The fluid container is positioned between a lens element and the wafer. The container is further characterized as having a substantially flexible and transparent bottom membrane contacting an upper surface of the wafer and overlapping at least one side edge of the wafer such that a fluid filled skirt is formed extending beyond the edges of the wafer.

摘要翻译： 一种使用改进的折射介质的光刻设备，系统和方法。 光刻设备可以用于浸入式光刻系统中，用于将光投射到诸如半导体晶片的工件上。 在一个实施例中，光刻设备包括容纳透明流体的容器。 流体容器位于透镜元件和晶片之间。 容器的特征还在于具有与晶片的上表面接触并且与晶片的至少一个侧边缘重叠的基本柔性且透明的底膜，从而形成延伸超过晶片边缘的充满流体的裙部。

公开(公告)号：US20050189655A1

公开(公告)日：2005-09-01

申请号：US10787640

申请日：2004-02-26

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

IPC分类号： H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间延伸的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US20050145803A1

公开(公告)日：2005-07-07

申请号：US10749638

申请日：2003-12-31

申请人： Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： G03F7/20 ,  H01L21/027 ,  G01J1/00

CPC分类号： G03F7/70341 ,  G03F7/70258

摘要： An apparatus for immersion optical lithography having a lens capable of relative movement in synchrony with a horizontal motion of a semiconductor wafer in a liquid environment where the synchronous motion of the lens apparatus and semiconductor wafer advantageously reduces the turbulence and air bubbles associated with a liquid environment. The relative motions of the lens and semiconductor wafer are substantially the same as the scanning process occurs resulting in optimal image resolution with minimal air bubbles, turbulence, and disruption of the liquid environment.

摘要翻译： 一种用于浸没式光刻的装置，其具有能够在液晶环境中与半导体晶片的水平运动同步的透镜的透镜，其中透镜装置和半导体晶片的同步运动有利地减少了与液体环境相关的湍流和气泡 。 透镜和半导体晶片的相对运动基本上与扫描过程相同，导致最小的图像分辨率，最小的气泡，湍流和液体环境的破坏。

公开(公告)号：US20050127466A1

公开(公告)日：2005-06-16

申请号：US10732958

申请日：2003-12-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L21/334 ,  H01L21/336 ,  H01L29/41 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/76 ,  H01L29/00

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78648

摘要： A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

摘要翻译： 形成具有环绕，垂直排列的双栅电极的场效应晶体管。 从具有掩埋硅岛的绝缘体上硅（SOI）结构开始，通过在SOI结构内产生空腔并在可以可靠地执行的两个回蚀步骤期间使用垂直参考边缘。 第一次回蚀将氧化物层的一部分去除第一距离，然后施加栅极导体材料。 第二次回蚀将栅极导体材料的一部分移除第二距离。 第一和第二距离之间的差异定义了最终设备的栅极长度。 剥离氧化物层后，显示出在所有四个侧表面上包围掩埋硅岛的垂直栅电极。

公开(公告)号：US20050286293A1

公开(公告)日：2005-12-29

申请号：US10879815

申请日：2004-06-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell

IPC分类号： G11C11/00 ,  G11C13/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/17 ,  H01L27/108 ,  H01L27/10861 ,  H01L27/10873 ,  Y10S977/742

摘要： A gain cell for a memory circuit, a memory circuit formed from multiple gain cells, and methods of fabricating such gain cells and memory circuits. The memory gain cell includes a storage capacitor, a write device electrically coupled with the storage capacitor for charging and discharging the storage capacitor to define a stored electrical charge, and a read device. The read device includes one or more semiconducting carbon nanotubes each electrically coupled between a source and drain. A portion of each semiconducting carbon nanotube is gated by the read gate and the storage capacitor to thereby regulate a current flowing through each semiconducting carbon nanotube from the source to the drain. The current is proportional to the electrical charge stored by the storage capacitor. In certain embodiments, the memory gain cell may include multiple storage capacitors.

摘要翻译： 用于存储器电路的增益单元，由多个增益单元形成的存储器电路，以及制造这种增益单元和存储器电路的方法。 存储增益单元包括存储电容器，与存储电容器电耦合以对存储电容器进行充电和放电以定义存储的电荷的写入装置和读取装置。 读取装置包括一个或多个半导体碳纳米管，每个碳纳米管电耦合在源极和漏极之间。 每个半导体碳纳米管的一部分由读取栅极和存储电容器选通，从而调节从源极到漏极流过每个半导体碳纳米管的电流。 电流与存储电容器存储的电荷成比例。 在某些实施例中，存储器增益单元可以包括多个存储电容器。

公开(公告)号：US20060292861A1

公开(公告)日：2006-12-28

申请号：US11458726

申请日：2006-07-20

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Mark Masters ,  Peter Mitchell ,  Stanislav Polonsky

IPC分类号： H01L21/4763

CPC分类号： B82Y10/00 ,  H01L21/28562 ,  H01L21/76877 ,  H01L23/5226 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： Conductive paths in an integrated circuit are formed using multiple undifferentiated carbon nanotubes embedded in a conductive metal, which is preferably copper. Preferably, conductive paths include vias running between conductive layers. Preferably, composite vias are formed by forming a metal catalyst pad on a conductor at the via site, depositing and etching a dielectric layer to form a cavity, growing substantially parallel carbon nanotubes on the catalyst in the cavity, and filling the remaining voids in the cavity with copper. The next conductive layer is then formed over the via hole.

摘要翻译： 集成电路中的导电路径使用嵌入导电金属中的多个未分化碳纳米管形成，优选为铜。 优选地，导电路径包括在导电层之间运行的通孔。 优选地，通过在通孔位置的导体上形成金属催化剂垫，沉积和蚀刻介电层以形成空腔，在空腔中的催化剂上基本上平行地生长碳纳米管，并填充其中的剩余空隙来形成复合通孔 有铜的腔。 然后在通孔上形成下一导电层。

公开(公告)号：US20050158673A1

公开(公告)日：2005-07-21

申请号：US10707894

申请日：2004-01-21

申请人： Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Mark Hakey ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： A61B18/18 ,  G03C5/10 ,  G03C5/20 ,  G03F7/20 ,  H01L21/00

CPC分类号： G03F7/70341 ,  Y10S438/947

摘要： A liquid-filled balloon may be positioned between a workpiece, such as a semiconductor structure covered with a photoresist, and a lithography light source. The balloon includes a thin membrane that exhibits good optical and physical properties. Liquid contained in the balloon also exhibits good optical properties, including a refractive index higher than that of air. Light from the lithography light source passes through a mask, through a top layer of the balloon membrane, through the contained liquid, through a bottom layer of the balloon membrane, and onto the workpiece where it alters portions of the photoresist. As the liquid has a low absorption and a higher refractive index than air, the liquid-filled balloon system enhances resolution. Thus, the balloon provides optical benefits of liquid immersion without the complications of maintaining a liquid between (and in contact with) a lithographic light source mechanism and workpiece.

摘要翻译： 液体填充的球囊可以位于诸如被光致抗蚀剂覆盖的半导体结构的工件和光刻光源之间。 气球包括显示出良好的光学和物理性质的薄膜。 包含在气囊中的液体也表现出良好的光学性能，包括折射率高于空气的折射率。 来自光刻光源的光通过球囊膜的顶层通过所包含的液体通过球囊膜的底层，并穿过其上改变部分光致抗蚀剂的工件。 由于液体具有比空气低的吸收和较高的折射率，所以充满液体的球囊系统提高了分辨率。 因此，气囊提供液体浸没的光学优点，而没有在平版印刷光源机构和工件之间（并与之接触）之间保持液体的并发症。

公开(公告)号：US20060289794A1

公开(公告)日：2006-12-28

申请号：US11160156

申请日：2005-06-10

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell

IPC分类号： G21G5/00

CPC分类号： G03F7/70341

摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

摘要翻译： 公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。 特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要 用于特殊镜头。 此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

公开(公告)号：US20070241408A1

公开(公告)日：2007-10-18

申请号：US11759981

申请日：2007-06-08

申请人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

发明人： Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/76229 ,  H01L21/823878 ,  H01L27/11

摘要： A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

摘要翻译： CMOS器件的良好隔离沟槽及其形成方法。 CMOS器件包括（a）半导体衬底，（b）半导体衬底中的P阱和N阱，（c）夹在P阱和N阱之间并与P阱和N阱直接物理接触的阱隔离区域。 P阱包括第一浅沟槽隔离（STI）区域，并且N阱包括第二STI区域。 阱隔离区域的底表面处于比第一和第二STI区域的底表面更低的水平面。 当从隔离区域的顶部到底部进行时，阱隔离区域的水平横截面的区域是基本上连续的函数。

公开(公告)号：US20070194403A1

公开(公告)日：2007-08-23

申请号：US11360345

申请日：2006-02-23

申请人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

发明人： Ethan Cannon ,  Toshiharu Furukawa ,  Mark Hakey ,  David Horak ,  Charles Koburger ,  Jimmy Kontos ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/76

CPC分类号： H01L27/0921 ,  H01L21/76229 ,  H01L21/823878

摘要： Semiconductor methods and device structures for suppressing latch-up in bulk CMOS devices. The method comprises forming a trench in the semiconductor material of the substrate with first sidewalls disposed between a pair of doped wells, also defined in the semiconductor material of the substrate. The method further comprises forming an etch mask in the trench to partially mask the base of the trench, followed by removing the semiconductor material of the substrate exposed across the partially masked base to define narrowed second sidewalls that deepen the trench. The deepened trench is filled with a dielectric material to define a trench isolation region for devices built in the doped wells. The dielectric material filling the deepened extension of the trench enhances latch-up suppression.

摘要翻译： 用于抑制大量CMOS器件中的闩锁的半导体方法和器件结构。 该方法包括在衬底的半导体材料中形成沟槽，其第一侧壁设置在也在衬底的半导体材料中定义的一对掺杂阱之间。 该方法还包括在沟槽中形成蚀刻掩模以部分地掩蔽沟槽的基底，随后去除暴露在部分屏蔽的基底上的衬底的半导体材料，以限定加深沟槽的变窄的第二侧壁。 加深的沟槽填充有介电材料以限定用于内置于掺杂阱中的器件的沟槽隔离区域。 填充沟槽加深的介质材料增强了闩锁抑制。