公开(公告)号：US20050179029A1

公开(公告)日：2005-08-18

申请号：US10777576

申请日：2004-02-12

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G11C13/02 ,  H01L21/336 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  G11C13/025 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/125 ,  H01L29/66409 ,  H01L29/772 ,  H01L51/0048 ,  Y10S977/734

摘要： A method for forming carbon nanotube field effect transistors, arrays of carbon nanotube field effect transistors, and device structures and arrays of device structures formed by the methods. The methods include forming a stacked structure including a gate electrode layer and catalyst pads each coupled electrically with a source/drain contact. The gate electrode layer is divided into multiple gate electrodes and at least one semiconducting carbon nanotube is synthesized by a chemical vapor deposition process on each of the catalyst pads. The completed device structure includes a gate electrode with a sidewall covered by a gate dielectric and at least one semiconducting carbon nanotube adjacent to the sidewall of the gate electrode. Source/drain contacts are electrically coupled with opposite ends of the semiconducting carbon nanotube to complete the device structure. Multiple device structures may be configured either as a memory circuit or as a logic circuit.

摘要翻译： 一种形成碳纳米管场效应晶体管的方法，碳纳米管场效应晶体管的阵列，以及通过该方法形成的器件结构和器件结构阵列。 所述方法包括形成包括栅极电极层和各个与源极/漏极接触电连接的催化剂焊盘的堆叠结构。 栅极电极层被分成多个栅极电极，并且通过化学气相沉积工艺在每个催化剂焊盘上合成至少一个半导体碳纳米管。 完成的器件结构包括具有由栅极电介质覆盖的侧壁的栅电极和与栅电极的侧壁相邻的至少一个半导体碳纳米管。 源极/漏极触点与半导体碳纳米管的相对端电耦合以完成器件结构。 多个器件结构可以被配置为存储器电路或逻辑电路。

公开(公告)号：US20050167655A1

公开(公告)日：2005-08-04

申请号：US10767065

申请日：2004-01-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： B82B1/00 ,  B82B3/00 ,  H01L27/28 ,  H01L51/05 ,  H01L51/30 ,  H01L51/40 ,  H01L29/06

CPC分类号： H01L51/057 ,  B82Y10/00 ,  H01L51/0048 ,  Y10S977/70 ,  Y10S977/734 ,  Y10S977/742

摘要： Vertical device structures incorporating at least one nanotube and methods for fabricating such device structures by chemical vapor deposition. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad and encased in a coating of a dielectric material. Vertical field effect transistors may be fashioned by forming a gate electrode about the encased nanotubes such that the encased nanotubes extend vertically through the thickness of the gate electrode. Capacitors may be fashioned in which the encased nanotubes and the corresponding catalyst pad bearing the encased nanotubes forms one capacitor plate.

摘要翻译： 结合至少一个纳米管的垂直器件结构和通过化学气相沉积制造这种器件结构的方法。 每个纳米管通过由催化剂垫催化的化学气相沉积生长并且包裹在电介质材料的涂层中。 可以通过围绕封装的纳米管形成栅电极来形成垂直场效应晶体管，使得封装的纳米管垂直延伸穿过栅电极的厚度。 可以形成电容器，其中包裹的纳米管和带有封装的纳米管的相应的催化剂垫片形成一个电容器板。

公开(公告)号：US20050202322A1

公开(公告)日：2005-09-15

申请号：US10798908

申请日：2004-03-11

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC分类号： G03F1/30

摘要： Methods for fabricating alternating phase shift masks or reticles used in semiconductor optical lithography systems. The methods generally include forming a layer of phase shift mask material on a handle substrate and patterning the layer to define recessed phase shift windows. The patterned layer is transferred from the handle wafer to a mask blank. The depth of the phase shift windows is determined by the thickness of the layer of phase shift mask material and is independent of the patterning process. In particular, the depth of the phase shift windows is not dependent upon the etch rate uniformity of an etch process across a surface of a mask blank.

摘要翻译： 用于制造用于半导体光刻系统中的交替相移掩模或掩模版的方法。 所述方法通常包括在手柄基板上形成一层相移掩模材料，并且图案化该层以限定凹陷的相移窗口。 图案层从手柄晶片转移到掩模板。 相移窗口的深度由相移掩模材料层的厚度确定，并且与图案化工艺无关。 特别地，相移窗口的深度不依赖于通过掩模板的表面的蚀刻工艺的蚀刻速率均匀性。

公开(公告)号：US20050167740A1

公开(公告)日：2005-08-04

申请号：US10767039

申请日：2004-01-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： H01L21/78 ,  H01L27/28 ,  H01L51/30 ,  H01L27/108

CPC分类号： H01L27/283 ,  B82Y10/00 ,  H01L51/0048 ,  H01L51/057 ,  Y10S977/70 ,  Y10S977/707 ,  Y10S977/721 ,  Y10S977/724

摘要： Vertical field effect transistors having a channel region defined by at least one semiconducting nanotube and methods for fabricating such vertical field effect transistors by chemical vapor deposition using a spacer-defined channel. Each nanotube is grown by chemical vapor deposition catalyzed by a catalyst pad positioned at the base of a high-aspect-ratio passage defined between a spacer and a gate electrode. Each nanotube grows in the passage with a vertical orientation constrained by the confining presence of the spacer. A gap may be provided in the base of the spacer remote from the mouth of the passage. Reactants flowing through the gap to the catalyst pad participate in nanotube growth.

摘要翻译： 具有由至少一个半导体纳米管限定的沟道区的垂直场效应晶体管以及通过使用间隔物定义的沟道的化学气相沉积来制造这种垂直场效应晶体管的方法。 每个纳米管通过化学气相沉积来生长，该催化剂垫位于位于间隔物和栅电极之间限定的高纵横比通道的基部处的催化剂垫。 每个纳米管在通道中生长，其中垂直取向受限于间隔物的限制。 可以在远离通道的口的间隔件的基部中设置间隙。 通过间隙流过催化剂垫的反应物参与纳米管生长。

公开(公告)号：US20050106472A1

公开(公告)日：2005-05-19

申请号：US10707009

申请日：2003-11-13

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger, III ,  Peter Mitchell ,  Larry Nesbit

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger, III ,  Peter Mitchell ,  Larry Nesbit

IPC分类号： B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  C23F3/00 ,  G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC分类号： G03F1/30 ,  G03F1/54 ,  G03F1/68

摘要： The invention provides a method of forming a phase shift mask and the resulting phase shift mask. The method forms a non-transparent film on a transparent substrate and patterns an etch stop layer on the non-transparent film. The invention patterns the non-transparent film using the etch stop layer to expose areas of the transparent substrate. Next, the invention forms a mask on the non-transparent film to protect selected areas of the transparent substrate and forms a phase shift oxide on exposed areas of the transparent substrate. Subsequently, the mask is removed and the phase shift oxide is polished down to the etch stop layer, after which the etch stop layer is removed.

摘要翻译： 本发明提供一种形成相移掩模的方法和所得到的相移掩模。 该方法在透明基板上形成不透明的薄膜，并在非透明薄膜上形成蚀刻停止层。 本发明使用蚀刻停止层来图案化非透明膜以暴露透明基底的区域。 接下来，本发明在非透明膜上形成掩模，以保护透明基板的选定区域，并在透明基板的曝光区域上形成相移氧化物。 随后，去除掩模并将相移氧化物抛光到蚀刻停止层，之后去除蚀刻停止层。

公开(公告)号：US20070184647A1

公开(公告)日：2007-08-09

申请号：US11735988

申请日：2007-04-16

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L21/4763

CPC分类号： B82Y10/00 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/842 ,  H01L2924/00

摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, depositing a conventional dielectric on the surface surrounding the carbon nanotubes, and then removing the carbon nanotubes to produce the voids. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. Recesses formed in the dielectric for conductors are lined with a non-conformal dielectric film to seal the voids. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.

摘要翻译： 集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。 优选地，通过首先形成垂直于集成电路晶片的表面的多个相对长的薄碳纳米管，在围绕碳纳米管的表面上沉积常规电介质，然后除去碳纳米管以产生空隙来形成空隙。 由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。 用于导体的电介质中形成的凹陷衬有非共形绝缘膜以密封空隙。 使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

公开(公告)号：US20060289794A1

公开(公告)日：2006-12-28

申请号：US11160156

申请日：2005-06-10

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Peter Mitchell

IPC分类号： G21G5/00

CPC分类号： G03F7/70341

摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.

摘要翻译： 公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。 特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要 用于特殊镜头。 此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

公开(公告)号：US20060022221A1

公开(公告)日：2006-02-02

申请号：US10901858

申请日：2004-07-29

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L29/768

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选包含两个碳纳米管子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，定向碳纳米管在反应物气体和催化剂的定向流的存在下在导电材料的表面上生长。

公开(公告)号：US20080042287A1

公开(公告)日：2008-02-21

申请号：US11924894

申请日：2007-10-26

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L23/52

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。

公开(公告)号：US20070048879A1

公开(公告)日：2007-03-01

申请号：US11552771

申请日：2006-10-25

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  Peter Mitchell

IPC分类号： H01L21/00

CPC分类号： H01L21/7685 ,  B82Y10/00 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53276 ,  H01L51/0048 ,  H01L51/0052 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/742 ,  Y10S977/762 ,  Y10S977/778 ,  Y10S977/842 ,  H01L2924/00

摘要： A conductive layer in an integrated circuit is formed as a sandwich having multiple sublayers, including at least one sublayer of oriented carbon nanotubes. The conductive layer sandwich preferably contains two sublayers of carbon nanotubes, in which the carbon nanotube orientation in one sublayer is substantially perpendicular to that of the other layer. The conductive layer sandwich preferably contains one or more additional sublayers of a conductive material, such as a metal. In one embodiment, oriented carbon nanotubes are created by forming a series of parallel surface ridges, covering the top and one side of the ridges with a catalyst inhibitor, and growing carbon nanotubes horizontally from the uncovered vertical sides of the ridges. In another embodiment, oriented carbon nanotubes are grown on the surface of a conductive material in the presence of a directional flow of reactant gases and a catalyst.

摘要翻译： 集成电路中的导电层形成为具有多个子层的夹层，包括至少一个定向碳纳米管子层。 导电层夹层优选含有碳纳米管的两个子层，其中一个子层中的碳纳米管取向基本上垂直于另一层的碳纳米管取向。 导电层夹层优选地包含一种或多种另外的导电材料的子层，例如金属。 在一个实施方案中，通过形成一系列平行的表面脊，通过用催化剂抑制剂覆盖脊的顶部和一侧并从脊的未被覆盖的垂直侧水平生长碳纳米管来产生定向碳纳米管。 在另一个实施方案中，在反应物气体和催化剂的定向流的存在下，在导电材料的表面上生长取向的碳纳米管。