公开(公告)号：US07336552B2

公开(公告)日：2008-02-26

申请号：US10927497

申请日：2004-08-27

Applicant: Martin Brox ,  Helmut Schneider

Inventor： Martin Brox ,  Helmut Schneider

IPC: G11C7/12

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C2207/005

Abstract: An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell field region, and for connecting/disconnecting the sense amplifier to/from from a bit line of a second cell field region, as a function of the state of control signals applied at control lines. Driver devices drive the control signal. Additional switches change the state of the control signals.

Abstract translation: 一种用于操作感测放大器连接/断开电路装置的装置和方法，特别是用于半导体存储器件，包括用于将读出放大器连接到/从第一单元区域的位线连接/断开读取放大器的开关装置，以及用于连接 根据在控制线处施加的控制信号的状态，将读出放大器与第二单元区域的位线断开/断开。 驱动器驱动控制信号。 附加开关改变控制信号的状态。

公开(公告)号：US20080012598A1

公开(公告)日：2008-01-17

申请号：US11457133

申请日：2006-07-12

Applicant: Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

Inventor： Peter Mayer ,  Wolfgang Spirkl ,  Markus Balb ,  Christoph Bilger ,  Martin Brox ,  Thomas Hein ,  Michael Richter

IPC: H03K19/003

CPC classification number: G11C7/1051 ,  G11C7/1048 ,  G11C7/1069 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50008 ,  H04L25/0278

Abstract: Method of controlling a driver strength and a termination impedance of a signal line of an interface, wherein the driver sends an output signal as an alternating voltage with a frequency, wherein the signal line is terminated with a termination impedance, wherein the driver strength is changed depending on a changing of the frequency of the output signal.

Abstract translation: 控制接口的信号线的驱动强度和终端阻抗的方法，其中所述驱动器将输出信号作为具有频率的交流电压发送，其中所述信号线以终端阻抗终止，其中所述驱动器强度改变 取决于输出信号频率的变化。

公开(公告)号：US20080010438A1

公开(公告)日：2008-01-10

申请号：US11752907

申请日：2007-05-23

Applicant: Wolfgang Spirkl ,  Martin Brox

Inventor： Wolfgang Spirkl ,  Martin Brox

IPC: G06F15/00

CPC classification number: G11C29/12 ,  G11C2029/0405 ,  G11C2029/3602

Abstract: The invention relates to a memory with a memory array with memory cells, with an input/output circuit which is connected to the memory cells and which interchanges data with the memory cells, with an output register which is connected to the input/output circuit, with the output register being used to output data via a data output, having an input register which is connected to a data input and to the input/output circuit, with the data input and the input register being used to input data into the memory cells, with test data being written to the output register in a test mode. The invention furthermore relates to a process for testing a memory and to a memory module.

Abstract translation: 本发明涉及具有存储器单元的存储器阵列的存储器，其中输入/输出电路连接到存储器单元并且与存储器单元交换数据，以及连接到输入/输出电路的输出寄存器， 其中输出寄存器用于经由数据输出输出数据，具有连接到数据输入端和输入/输出电路的输入寄存器，数据输入端和输入寄存器用于将数据输入存储单元 测试数据以测试模式写入输出寄存器。 本发明还涉及一种用于测试存储器和存储器模块的过程。

公开(公告)号：US20070182468A1

公开(公告)日：2007-08-09

申请号：US11211084

申请日：2005-08-25

Applicant: Martin Brox ,  Alessandro Minzoni

Inventor： Martin Brox ,  Alessandro Minzoni

IPC: H03L7/06

CPC classification number: H03K5/135

Abstract: The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device (101) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means (102) with a variably controllable delay time (tvar), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (tvar), and is output as delayed clock signal, a phase comparator (104) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means (401, 116) is provided for activating and/or deactivating said clock signal synchronizing device (101) as a function of control signals (RD) evaluated by an evaluating means (402).

Abstract translation: 本发明涉及一种时钟信号同步方法以及与时钟信号（CLK，DQS）的同步一起使用的时钟信号同步装置（101），包括：具有可变可控延迟时间的延迟装置（102） 其中输入了时钟信号（CLK）或从其获得的信号）被加载了可变可控延迟时间（t> var ），并被输出 作为延迟时钟信号，用于将时钟信号（CLK）的相位或由其获得的信号与延迟的时钟信号的相位或从其获得的信号（DCLK，FB）进行比较的相位比较器（104），其特征在于 另外还提​​供了一种用于根据由评估装置（402）评估的控制信号（RD）来激活和/或去激活所述时钟信号同步装置（101）的装置（401,116）。

公开(公告)号：US20070153615A1

公开(公告)日：2007-07-05

申请号：US10569859

申请日：2004-07-09

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G11C8/00

CPC classification number: G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4096

Abstract: A method for operating a semiconductor memory device is disclosed. In one embodiment, the method includes activating a first memory cell sub-array or memory cells of the first memory cell sub-array that are contained in a first set of memory cells, in particular of memory cells positioned in one and the same row or column of the first memory cell sub-array, if one or a plurality of memory cells contained in the first memory cell sub-array or in the first set of memory cells is/are to be accessed. The corresponding memory cell or memory cells are accessed; including leaving the first memory cell sub-array or the memory cells of the first memory cell sub-array that are contained in the first set of memory cells in the activated state if one or a plurality of further memory cells is/are to be accessed which are contained in a second memory cell sub-array of the same memory cell array that comprises the first memory cell sub-array.

Abstract translation: 公开了一种用于操作半导体存储器件的方法。 在一个实施例中，该方法包括激活包含在第一组存储器单元中的第一存储单元子阵列的第一存储单元子阵列或存储器单元，特别是位于同一行中的存储器单元或 如果第一存储单元子阵列中包含的一个或多个存储单元或第一组存储器单元中的一个或多个存储器单元将被访问，则第一存储单元子阵列的列将被访问。 访问相应的存储单元或存储单元; 包括如果要访问一个或多个另外的存储器单元，则将处于激活状态的包含在第一组存储器单元中的第一存储单元子阵列或第一存储单元子阵列的存储单元留下 其包含在包括第一存储单元子阵列的相同存储单元阵列的第二存储单元子阵列中。

公开(公告)号：US06954099B2

公开(公告)日：2005-10-11

申请号：US10613381

申请日：2003-07-03

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G05F5/08 ,  G11C7/10 ,  H03G3/00 ,  H03K3/356 ,  H03K5/01 ,  H03L5/00

CPC classification number: G11C7/1084 ,  G11C7/1078 ,  H03K3/356113 ,  H03K3/356147

Abstract: The invention involves a voltage converter device (101a, 101b) for converting a signal (in) at an initial voltage level (vint) into a signal (DatoV) at a second voltage level (vint) differing from the first, in which voltage converter device (101a, 101b) has an amplifier device (102), and where the amplifier device (102) uses a second amplifier device output signal (bout) to generate signals (DatoV) at the second voltage level (vddq).

Abstract translation: 本发明涉及一种用于将初始电压电平（vint）的信号（in）转换为不同于第一电压电平（vint）的信号（DatoV）的电压转换器装置（101a，101b），其中 电压转换器装置（101a，101b）具有放大器装置（102），并且其中放大器装置（102）使用第二放大器装置输出信号（bout）来产生处于第二电压电平（vddq）的信号（DatoV） 。

公开(公告)号：US20050117435A1

公开(公告)日：2005-06-02

申请号：US10927497

申请日：2004-08-27

Applicant: Martin Brox ,  Helmut Schneider

Inventor： Martin Brox ,  Helmut Schneider

IPC: G11C7/06 ,  G11C11/4091 ,  G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C2207/005

Abstract: The invention relates to a method for operating a sense amplifier connecting/disconnecting circuit arrangement, and to a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting a sense amplifier device to a bit line or to a cell field region, respectively, and for disconnecting the sense amplifier device from the bit line or from the cell field region, respectively, as a function of the state of a control signal applied at a control line; a driver device for driving the control signal, wherein an additional device, in particular an additional switch is provided, by means of which a change of state of the control signal applied at the control line can be effected.

Abstract translation: 本发明涉及一种用于操作读出放大器连接/断开电路装置的方法，以及一种用于读出放大器连接/断开电路装置的方法，特别是涉及一种半导体存储器件，包括用于将读出放大器器件连接到位线 或者分别连接到单元场区域，并且用于分别根据在控制线处施加的控制信号的状态来将读出放大器装置分别从位线或单元场区域断开; 用于驱动控制信号的驱动器装置，其中提供附加装置，特别是附加开关，通过该装置可以实现在控制线处施加的控制信号的状态改变。

公开(公告)号：US20050052913A1

公开(公告)日：2005-03-10

申请号：US10892546

申请日：2004-07-16

Applicant: Martin Brox

Inventor： Martin Brox

IPC: G11C7/10 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4093 ,  G11C7/00

CPC classification number: G11C7/109 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C11/4093

Abstract: The invention relates to a semi-conductor memory component and process for operating a semi-conductor memory component, including activating the memory cells of a memory cell array, when one or several memory cell(s) included in the first set of memory cells need(s) to be accessed, accessing the corresponding memory cell or memory cells, deactivating the memory cells contained in a first set of memory cells, when one or several further memory cells that are not included in the first set of memory cells need(s) to be accessed, and prematurely deactivating the memory cells included in the first set of memory cells, when a predetermined time period or number of pulses after one or several memory cells included in the first set of memory cells have last been accessed first no further accessing of one or several of the memory cells included in the first set of memory cells takes place.

Abstract translation: 本发明涉及半导体存储器组件和用于操作半导体存储器组件的过程，包括在第一组存储器单元中包括的一个或多个存储单元需要时激活存储单元阵列的存储单元 （第一组存储器单元中的一个或多个另外的存储器单元需要（s））时，访问对应的存储器单元或存储器单元，停用包含在第一组存储器单元中的存储器单元 ），并且当在第一组存储器单元中包括的一个或多个存储器单元之后的预定时间段或脉冲数最后被首先访问时，过早地使包括在第一组存储器单元中的存储器单元去激活。 发生包含在第一组存储器单元中的一个或多个存储单元的存取。

公开(公告)号：US06765421B2

公开(公告)日：2004-07-20

申请号：US10393525

申请日：2003-03-20

Applicant: Martin Brox ,  Alessandro Minzoni

Inventor： Martin Brox ,  Alessandro Minzoni

IPC: H03K3017

CPC classification number: G06F1/06 ,  H03K5/133 ,  H03K5/1565 ,  H03K2005/00039 ,  H03L7/07 ,  H03L7/0812

Abstract: An apparatus for generating two signals having a predetermined spacing between mutually corresponding signal edges includes first and second delay devices for delaying a clock signal and a complementary clock signal in response to respective first and second control signals. A first control signal generator generates the first control signal on the basis of the clock signal and the delayed clock signal. A second control signal generator generates the second control signal on the basis of the delayed clock signal and the delayed complementary clock signal. The second control signal generator causes the delayed clock signal and the delayed complementary clock signal to have a steady-state condition in which mutually corresponding edges thereof are separated by a pre-determined spacing.

Abstract translation: 用于产生具有相互相应的信号边缘之间的预定间隔的两个信号的装置包括用于响应于相应的第一和第二控制信号延迟时钟信号和互补时钟信号的第一和第二延迟装置。 第一控制信号发生器基于时钟信号和延迟的时钟信号产生第一控制信号。 第二控制信号发生器基于延迟的时钟信号和延迟的互补时钟信号产生第二控制信号。 第二控制信号发生器使得延迟的时钟信号和延迟的互补时钟信号具有稳态状态，其中相互对应的边缘被分隔预定的间隔。

公开(公告)号：US06700426B2

公开(公告)日：2004-03-02

申请号：US10302864

申请日：2002-11-25

Applicant: Martin Brox ,  Bernd Klehn ,  Joachim Schnabel

Inventor： Martin Brox ,  Bernd Klehn ,  Joachim Schnabel

IPC: H03L500

CPC classification number: H02M3/07 ,  G11C5/145

Abstract: Programmable voltage pump for producing an output voltage includes a trim input configured to set the output voltage, an output configured to emit the output voltage therefrom, and an activation/deactivation input configured to at least one of activate and deactivate the voltage pump. The activation/deactivation input includes a switch connected to the output, the switch configured to selectively connect a network to ground, the network being connected to the output.

Abstract translation: 用于产生输出电压的可编程电压泵包括配置为设置输出电压的调整输入，被配置为从其发射输出电压的输出以及被配置为激活和去激活电压泵中的至少一个的激活/去激活输入。 激活/去激活输入包括连接到输出的交换机，交换机被配置为选择性地将网络连接到地，网络连接到输出。