公开(公告)号：US5918139A

公开(公告)日：1999-06-29

申请号：US14415

申请日：1998-01-27

申请人： Kiyoshi Mitani ,  Katsuo Yoshizawa

发明人： Kiyoshi Mitani ,  Katsuo Yoshizawa

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/20 ,  H01L21/304 ,  H01L27/12 ,  H01L21/30 ,  H01L21/46

CPC分类号： H01L21/2007

摘要： A method of manufacturing a bonding substrate is disclosed. An oxide film is formed on the surface of at least one of two semiconductor substrates, and the two substrates are brought into close contact with each other via the oxide film. The substrates are heat-treated in an oxidizing atmosphere in order to firmly join the substrates together. Subsequently, an unjoined portion at the periphery of a device-fabricating substrate is completely removed, and the thickness of the device-fabricating substrate is reduced to a desired thickness so as to yield a thin film. The surface of the thin film is then etched through vapor-phase etching in order to make the thickness of the thin film uniform. In the method, the oxide film on the unjoined portion of at least the support substrate is removed before the surface of the thin film is subjected to vapor-phase etching. The method prevents a groove from being formed in the surface of the unjoined portion (terrace portion) of the support substrate (base wafer) even when the surface of the thin film undergoes vapor phase etching.

摘要翻译： 公开了一种制造接合衬底的方法。 在两个半导体衬底中的至少一个的表面上形成氧化物膜，并且通过氧化膜使两个衬底彼此紧密接触。 将基板在氧化气氛中进行热处理，以将基板牢固地接合在一起。 随后，在器件制造衬底的周边处的未连接部分被完全去除，并且将器件制造衬底的厚度减小到期望的厚度以产生薄膜。 然后通过气相蚀刻对薄膜的表面进行蚀刻，以使薄膜的厚度均匀。 在该方法中，在对薄膜的表面进行气相蚀刻之前，去除至少支撑基板的未连接部分上的氧化膜。 即使当薄膜的表面进行气相蚀刻时，该方法也防止在支撑基板（基底晶片）的未连接部分（平台部分）的表面中形成凹槽。

公开(公告)号：USD398008S

公开(公告)日：1998-09-08

申请号：US79041

申请日：1997-11-07

申请人： Yasuki Yamakawa ,  Kiyoshi Mitani

设计人： Yasuki Yamakawa ,  Kiyoshi Mitani

公开(公告)号：US5650353A

公开(公告)日：1997-07-22

申请号：US561166

申请日：1995-11-21

申请人： Katsuo Yoshizawa ,  Tsutomu Sato ,  Kiyoshi Mitani ,  Masatake Katayama

发明人： Katsuo Yoshizawa ,  Tsutomu Sato ,  Kiyoshi Mitani ,  Masatake Katayama

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/304 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  Y02P80/30 ,  Y10S148/012 ,  Y10S148/135

摘要： SOI (silicon-on-insulator) substrates are efficiently produced by a method which comprises superposing and bonding at least three single crystal silicon wafers through the medium of a SiO.sub.2 film formed on the surface of each of the wafers and cutting the bonded wafers along planes perpendicular to the direction of superposition thereof. The cutting can be infallibly attained with high dimensional accuracy without entailing such adverse phenomena as the vibration of the blade of a cutting tool by providing at the portions destined to be cut the grooves for guiding the blade of the cutting tool in advance of the cutting work.

摘要翻译： 通过一种方法有效地制造SOI（绝缘体上硅）衬底，该方法包括通过形成在每个晶片的表面上的SiO 2膜的介质将至少三个单晶硅晶片叠加并结合，并沿着平面切割结合的晶片 垂直于其叠加方向。 可以以高尺寸精度实现切割，而不会产生诸如切割工具的刀片的振动的不利现象，因为在切割工具的前面提供用于引导切割工具的刀刃的凹槽的部分 。

公开(公告)号：US5578504A

公开(公告)日：1996-11-26

申请号：US275540

申请日：1994-07-15

申请人： Kiyoshi Mitani ,  Shigenori Saisu

发明人： Kiyoshi Mitani ,  Shigenori Saisu

IPC分类号： G01N27/04 ,  G01R27/02 ,  G01R27/14 ,  H01L21/66

CPC分类号： G01R27/14 ,  H01L22/14 ,  Y10S148/146 ,  Y10S438/934 ,  Y10S438/974

摘要： A method for the determination of the resistivity of an n-type epitaxial layer formed on a silicon substrate is disclosed. This invention resides in either directly determining the true resistivity of a sample by preparing this sample without a natural oxide film which is responsible for the change with the passage of time or indirectly determining the true resistivity of a sample by intentionally forming on the sample a natural oxide film so stable to defy the change with the passage of time and measuring resistivity of this sample.

摘要翻译： 公开了一种用于确定在硅衬底上形成的n型外延层的电阻率的方法。 本发明在于直接确定样品的真实电阻率，通过制备该样品而不使用天然氧化物膜，其负责随着时间的推移而改变，或间接地通过在样品上形成天然物来确定样品的真实电阻率 氧化膜如此稳定以抵抗随时间的变化和测量该样品的电阻率。

公开(公告)号：US5514235A

公开(公告)日：1996-05-07

申请号：US262113

申请日：1994-06-17

申请人： Kiyoshi Mitani ,  Masatake Katayama

发明人： Kiyoshi Mitani ,  Masatake Katayama

IPC分类号： H01L21/02 ,  B81C1/00 ,  H01L21/20 ,  H01L21/324 ,  H01L27/12 ,  H01L21/304

CPC分类号： H01L21/2007 ,  Y10S148/012 ,  Y10S148/135

摘要： A method is disclosed for obtaining bonded wafers of SOI type, where impurity redistribution in the bulk of the wafers is suppressed and the bonding strength between the wafers is substantially higher compared with that in the prior art. This is accomplished by forming a thermally grown oxide layer on the surface of the thinner one(bond wafer) of two monocrystalline silicon wafers having thicknesses different from each other by more than 50 .mu.m; then superposing the thinner wafer onto the other thicker wafer(base wafer); and finally conducting at least two heat treatments of the wafers at temperatures selected in the range of under 900.degree. C. for a period of time selected in the range of from 0.5 min. to 120 min.

摘要翻译： 公开了一种用于获得SOI类型的接合晶片的方法，其中抑制了大部分晶片中的杂质再分布，并且晶片之间的结合强度与现有技术相比显着更高。 这是通过在具有彼此不同的厚度大于50μm的两个单晶硅晶片的较薄的一个（接合晶片）的表面上形成热生长的氧化物层来实现的; 然后将较薄的晶片叠加到另一个较厚的晶片（基底晶片）上; 并且最后在900℃以下选择的温度下进行晶片的至少两次热处理一段时间，其选择范围为0.5分钟。 至120分钟

公开(公告)号：US5306939A

公开(公告)日：1994-04-26

申请号：US56816

申请日：1993-04-28

申请人： Kiyoshi Mitani ,  Witawat Wijaranakula

发明人： Kiyoshi Mitani ,  Witawat Wijaranakula

IPC分类号： H01L27/092 ,  H01L27/02

CPC分类号： H01L27/0925 ,  H01L27/0921

摘要： The present invention is a CMOS epitaxial silicon wafer (50) on which CMOS integrated circuits (16) can be manufactured, including such circuits that include bipolar components (referred to as "BiCMOS" circuits). The CMOS wafer includes a lightly doped monocrystalline silicon substrate (56) having a major surface (54) that supports a lightly doped monocrystalline epitaxial silicon layer (52). The substrate includes a heavily doped diffused layer (58) extending a short distance (64) into the substrate from the major surface toward a lightly doped bulk portion (66) of the substrate. CMOS integrated circuits manufactured on the epitaxial layer of the CMOS wafer of this invention have a low susceptibility to latch-up. The low susceptibility is provided by the relatively low resistivity of the diffused layer. Since the diffused layer is relatively thin and the bulk portion is lightly doped, the oxygen content of the bulk can be readily measured and controlled.

摘要翻译： 本发明是一种可以制造CMOS集成电路（16）的CMOS外延硅晶片（50），包括包括双极组件（称为“BiCMOS”电路）的电路。 CMOS晶片包括具有支撑轻掺杂单晶外延硅层（52）的主表面（54）的轻掺杂单晶硅衬底（56）。 衬底包括从衬底的主表面向衬底的轻掺杂体部分（66）延伸短距离（64）到衬底中的重掺杂扩散层（58）。 在本发明的CMOS晶片的外延层上制造的CMOS集成电路具有低的闩锁敏感性。 低磁化率由扩散层的较低电阻率提供。 由于扩散层相对较薄并且本体部分被轻掺杂，因此容易测量和控制本体的氧含量。

公开(公告)号：USD278629S

公开(公告)日：1985-04-30

申请号：US389795

申请日：1982-06-18

申请人： Kiyoshi Mitani ,  Hiroshi Yonekura ,  Kiyoshi Suzuki ,  Osamu Sugihara

设计人： Kiyoshi Mitani ,  Hiroshi Yonekura ,  Kiyoshi Suzuki ,  Osamu Sugihara