公开(公告)号：US5650353A

公开(公告)日：1997-07-22

申请号：US561166

申请日：1995-11-21

申请人： Katsuo Yoshizawa ,  Tsutomu Sato ,  Kiyoshi Mitani ,  Masatake Katayama

发明人： Katsuo Yoshizawa ,  Tsutomu Sato ,  Kiyoshi Mitani ,  Masatake Katayama

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/304 ,  H01L21/762 ,  H01L27/12

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  Y02P80/30 ,  Y10S148/012 ,  Y10S148/135

摘要： SOI (silicon-on-insulator) substrates are efficiently produced by a method which comprises superposing and bonding at least three single crystal silicon wafers through the medium of a SiO.sub.2 film formed on the surface of each of the wafers and cutting the bonded wafers along planes perpendicular to the direction of superposition thereof. The cutting can be infallibly attained with high dimensional accuracy without entailing such adverse phenomena as the vibration of the blade of a cutting tool by providing at the portions destined to be cut the grooves for guiding the blade of the cutting tool in advance of the cutting work.

摘要翻译： 通过一种方法有效地制造SOI（绝缘体上硅）衬底，该方法包括通过形成在每个晶片的表面上的SiO 2膜的介质将至少三个单晶硅晶片叠加并结合，并沿着平面切割结合的晶片 垂直于其叠加方向。 可以以高尺寸精度实现切割，而不会产生诸如切割工具的刀片的振动的不利现象，因为在切割工具的前面提供用于引导切割工具的刀刃的凹槽的部分 。

公开(公告)号：US5514235A

公开(公告)日：1996-05-07

申请号：US262113

申请日：1994-06-17

申请人： Kiyoshi Mitani ,  Masatake Katayama

发明人： Kiyoshi Mitani ,  Masatake Katayama

IPC分类号： H01L21/02 ,  B81C1/00 ,  H01L21/20 ,  H01L21/324 ,  H01L27/12 ,  H01L21/304

CPC分类号： H01L21/2007 ,  Y10S148/012 ,  Y10S148/135

摘要： A method is disclosed for obtaining bonded wafers of SOI type, where impurity redistribution in the bulk of the wafers is suppressed and the bonding strength between the wafers is substantially higher compared with that in the prior art. This is accomplished by forming a thermally grown oxide layer on the surface of the thinner one(bond wafer) of two monocrystalline silicon wafers having thicknesses different from each other by more than 50 .mu.m; then superposing the thinner wafer onto the other thicker wafer(base wafer); and finally conducting at least two heat treatments of the wafers at temperatures selected in the range of under 900.degree. C. for a period of time selected in the range of from 0.5 min. to 120 min.

摘要翻译： 公开了一种用于获得SOI类型的接合晶片的方法，其中抑制了大部分晶片中的杂质再分布，并且晶片之间的结合强度与现有技术相比显着更高。 这是通过在具有彼此不同的厚度大于50μm的两个单晶硅晶片的较薄的一个（接合晶片）的表面上形成热生长的氧化物层来实现的; 然后将较薄的晶片叠加到另一个较厚的晶片（基底晶片）上; 并且最后在900℃以下选择的温度下进行晶片的至少两次热处理一段时间，其选择范围为0.5分钟。 至120分钟

公开(公告)号：US5998281A

公开(公告)日：1999-12-07

申请号：US698457

申请日：1996-08-15

申请人： Hiroji Aga ,  Kiyoshi Mitani ,  Masatake Katayama

发明人： Hiroji Aga ,  Kiyoshi Mitani ,  Masatake Katayama

IPC分类号： H01L21/20 ,  H01L21/762

CPC分类号： H01L21/76251 ,  H01L21/2007 ,  Y10S148/012 ,  Y10S438/977

摘要： Proposed is an improvement in the process for the preparation of an SOI wafer comprising the steps of: forming an oxidized surface film on the mirror-polished surface of a first mirror-polished semiconductor silicon wafer as the base wafer; forming a doped layer with a dopant in a high concentration on the mirror-polished surface of a second mirror-polished semiconductor silicon wafer as the bond wafer; bringing the base wafer and the bond wafer into contact each with the other at the oxidized surface film and the doped layer; and subjecting the thus contacted semiconductor silicon wafers to a heat treatment to effect integral bonding thereof into a precursor of an SOI wafer. The improvement of the invention is accomplished by polishing the surface of the doped layer on the bond wafer before the base wafer and the bond wafer are joined by contacting at the oxidized surface film and the doped layer so that a great improvement can be obtained in the bonding strength between layers.

摘要翻译： 提出了制备SOI晶片的方法的改进，包括以下步骤：在作为基底晶片的第一镜面抛光半导体硅晶片的镜面抛光表面上形成氧化的表面膜; 在作为接合晶片的第二镜面抛光半导体硅晶片的镜面抛光表面上形成具有高浓度掺杂剂的掺杂层; 使基底晶片和接合晶片在氧化的表面膜和掺杂层处彼此接触; 以及对这样接触的半导体硅晶片进行热处理以使其整体结合到SOI晶片的前体中。 通过在基底晶片和接合晶片通过在氧化的表面膜和掺杂层之间接触而接合基底晶片和接合晶片之前，通过抛光接合晶片上的掺杂层的表面来实现本发明的改进，使得可以在 层之间的粘结强度。

公开(公告)号：US5804494A

公开(公告)日：1998-09-08

申请号：US694861

申请日：1996-08-09

申请人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

发明人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/304 ,  H01L21/306 ,  H01L21/324 ,  H01L21/762 ,  H01L27/12 ,  H01L21/30

CPC分类号： H01L21/02043 ,  H01L21/2007 ,  H01L21/76251 ,  Y10S148/012

摘要： A method of fabricating a bonded wafer which is capable of reducing the concentrations of impurities, and more particularly the boron concentration, at the interface of bonding in the bonded wafer, wherein first and second wafers to be bonded are finish-cleaned, then the wafers are temporarily stored in a closed box so as to isolate the wafers from clean-room air, thereafter the first and second wafers are superposed in a clean atmosphere which is held out of direct contact with clean-room air, and finally the superposed first and second wafers are bonded together by a heat-treatment.

摘要翻译： 一种制造接合晶片的方法，该方法能够在键合晶片的接合界面处降低杂质浓度，特别是硼浓度，其中待结合的第一和第二晶片经过精整处理，然后晶片 临时储存在封闭的箱体中，以将晶片与洁净室空气隔离，此后第一和第二晶片重叠在与洁净室空气直接接触的清洁气氛中，最后重叠在第一和第 第二片通过热处理结合在一起。

公开(公告)号：US5538904A

公开(公告)日：1996-07-23

申请号：US310397

申请日：1994-09-22

申请人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

发明人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

IPC分类号： H01L21/66 ,  H01L21/02 ,  H01L21/762

CPC分类号： H01L21/76251 ,  Y10S148/012

摘要： A method of estimating the amount of boron on the surface of silicone samples in which a plurality of reference samples shallowly ion-implanted with boron in different dosages are prepared and heat-treated under the same conditions of temperature and time as are used in a bonding heat treatment to obtain the bonded wafer, thereafter, the boron profile in the direction of the depth of the bonding interface in each reference sample is measured using a SIMS and compared with an actual boron profile at the bonding interface of a bonded wafer to be estimated so as to determine one reference sample whose boron profile is equivalent to the actual boron profile of the bonded wafer to be estimated, and finally a dosage of boron in the determined reference sample is estimated by convertion to be a surface density of boron presenting at the bonding interface of the bonded wafer to be estimated at an initial stage prior to the bonding heat treatment of the bonded wafer to be estimated. Thus, the boron profile obtained by SIMS measurement can be converted into the boron surface density with the result that the boron quantity at the bonding interface of a bonded wafer can be readily estimated to be a boron surface density.

摘要翻译： 一种估计硅胶样品表面上硼的量的方法，其中以与不同剂量的硼浅离子注入的多个参考样品制备并在与粘合中使用的相同的温度和时间条件下进行热处理 热处理以获得接合的晶片，此后，使用SIMS测量每个参考样品中的接合界面的深度方向上的硼分布，并与待估计的键合晶片的键合界面处的实际硼分布进行比较 以便确定一个参考样品，其硼分布等于要估计的键合晶片的实际硼分布，最后通过转换来估计所确定的参考样品中的硼剂量，使其为硼的表面密度 接合晶片的接合界面在待估计的接合晶片的接合热处理之前的初始阶段被估计。 因此，通过SIMS测量获得的硼分布可以转化为硼表面密度，结果是接合晶片的键合界面处的硼量可以容易地估计为硼表面密度。

公开(公告)号：US5478408A

公开(公告)日：1995-12-26

申请号：US408798

申请日：1995-03-23

申请人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

发明人： Kiyoshi Mitani ,  Masatake Katayama ,  Kazushi Nakazawa

IPC分类号： H01L21/762 ,  H01L21/02 ,  H01L21/20 ,  H01L21/322 ,  H01L27/12 ,  H01L21/265

CPC分类号： H01L21/2007 ,  H01L21/3225 ,  Y10S148/012

摘要： There is provided an SOI (Silicon On Insulator) substrate having a thick SOI layer, where crystallographic defects mainly consisting of OSFs (Oxidation Induced Stacking Fault) are practically prevented from occurrence in the SOI layer, according to the present invention.The manufacturing method for the SOI substrate according to the present invention comprises the following steps of: the silicon oxide film being formed by thermal oxidation on the surface of a first silicon wafer having a concentration of interstitial oxygen under 16 ppma (per JEIDA Standard); the first silicon wafer being superimposed on a second silicon wafer, which is a support for supporting the first silicon wafer, with the silicon oxide film sandwiched therebetween; then the superimposed wafers being heat-treated so as to obtain a bonded wafer; and further the bulk of the first silicon wafer of the bonded wafer being reduced by grinding and then polishing so as to obtain the SOI substrate with the SOI layer of more than 5 .mu.m in thickness, which is a single crystal layer, formed on the second silicon wafer.

摘要翻译： 根据本发明，提供了具有厚SOI层的SOI（绝缘体上硅）衬底，其中实际上防止了在SOI层中出现主要由OSF（氧化诱发堆叠故障）组成的晶体缺陷。 根据本发明的SOI衬底的制造方法包括以下步骤：在具有16ppma（根据JEIDA标准）的间隙氧浓度的第一硅晶片的表面上通过热氧化形成氧化硅膜; 所述第一硅晶片叠加在第二硅晶片上，所述第二硅晶片是用于支撑所述第一硅晶片的支撑体，其间夹置有所述氧化硅膜; 然后对叠加的晶片进行热处理以获得接合晶片; 并且通过研磨然后抛光来还原接合晶片的第一硅晶片的大部分，以获得厚度大于5μm的SOI层（其是形成在单晶层上的单晶层）的SOI衬底 第二硅晶片。

公开(公告)号：US5696034A

公开(公告)日：1997-12-09

申请号：US520189

申请日：1995-08-28

申请人： Masatake Katayama ,  Isao Moroga ,  Isao Shirai ,  Youichi Kumaki ,  Akio Kasahara

发明人： Masatake Katayama ,  Isao Moroga ,  Isao Shirai ,  Youichi Kumaki ,  Akio Kasahara

IPC分类号： H01L29/78 ,  H01L21/18 ,  H01L21/20 ,  H01L21/205 ,  H01L21/304 ,  H01L21/331 ,  H01L21/336 ,  H01L29/739 ,  H01L21/465

CPC分类号： H01L29/66333 ,  H01L21/187 ,  Y10S148/135

摘要： A method for producing a semiconductor substrate in which no autodoping occurs and slip dislocations in the substrate are reduced. The method involves forming a silicon nitride film on the backside of an n.sup.- -silicon substrate, epitaxially growing an n.sup.+ -buffer layer and a p.sup.+ -layer on the front side of the n.sup.- -silicon substrate, and decreasing the thickness of the n.sup.- -silicon substrate from the backside.

摘要翻译： 不产生自动掺杂的半导体衬底的制造方法和衬底中的滑移位错减小。 该方法包括在n - 硅衬底的背面上形成氮化硅膜，在n-硅衬底的正面外延生长n +缓冲层和p +层，并减小n 硅衬底从背面。

公开(公告)号：US5183783A

公开(公告)日：1993-02-02

申请号：US811958

申请日：1991-12-23

申请人： Yutaka Ohta ,  Konomu Ohki ,  Masatake Katayama

发明人： Yutaka Ohta ,  Konomu Ohki ,  Masatake Katayama

IPC分类号： H01L21/762

CPC分类号： H01L21/76297 ,  Y10S438/928 ,  Y10S438/977

摘要： Single crystal silicon islands in a dielectric-separation substrate are separated completely and finished in a uniform thickness by preparatorily denuding a single crystal silicon substrate of a warpage suffered to occur therein.This dielectric-separation substrate is produced by a method which comprises forming a thermal oxide film on a single crystal silicon substrate having grooves incised in advance therein, then forming an irreversibly thermally shrinkable film on the rear surface of said single crystal silicon substrate prior to depositing a polycrystalline silicon thereon, then depositing a polycrystalline silicon on said single crystal silicon substrate, and thereafter grinding said single crystal silicon substrate in conjunction with said irreversibly thermally shrinkable film.

公开(公告)号：US6048793A

公开(公告)日：2000-04-11

申请号：US546868

申请日：1995-10-23

申请人： Hitoshi Habuka ,  Masanori Mayuzumi ,  Naoto Tate ,  Masatake Katayama

发明人： Hitoshi Habuka ,  Masanori Mayuzumi ,  Naoto Tate ,  Masatake Katayama

IPC分类号： C23C16/24 ,  C23C16/02 ,  C23C16/44 ,  C23C16/455 ,  C23C16/48 ,  C30B25/10 ,  H01L21/205 ,  C23C16/01

CPC分类号： C23C16/481 ,  C23C16/0209 ,  C23C16/0236 ,  C23C16/4401 ,  C30B25/10

摘要： In a method and an appratus for a thin film growth on a semiconductor crystal substrate, impurities and contaminants absorbed on the inside wall of the reaction vessel are very harmful because these impurities and contaminants will deteriorate the quality of the thin film. A method and an apparatus by which the quantity of these impurities and contaminants absorbed on the inside wall of the reaction vessel can be restrained and removed easily are disclosed in this invention, wherein a semiconductor crystal substrate is mounted in the reaction vessel, and the wall of the reation vessel is cooled forcibly by a coolant while the substrate is under heating procedure to grow a thin film on the substrate by supplying the raw material gas into the reaction vessel. And the temperature of the wall of the reaction vessel during the procedure except the thin film growth is kept higher temperature than the temprature of the wall of the reaction vessel during the thin film growth procedure.

摘要翻译： 在半导体晶体基板上的薄膜生长的方法和设备中，吸收在反应容器的内壁上的杂质和污染物是非常有害的，因为这些杂质和污染物将使薄膜的质量劣化。 在本发明中公开了容易地抑制和去除反应容器的内壁上吸收的这些杂质和污染物的量的方法和装置，其中半导体晶体基板安装在反应容器中，壁 的反应容器被冷却剂强制冷却，同时衬底处于加热过程中，以通过将原料气体供应到反应容器中而在衬底上生长薄膜。 并且在薄膜生长过程中除了薄膜生长之外，反应容器的壁温度保持比反应容器壁温度高的温度。

公开(公告)号：US5759426A

公开(公告)日：1998-06-02

申请号：US558540

申请日：1995-11-16

申请人： Norihiro Kobayashi ,  Kazuo Mamada ,  Yuichi Matsumoto ,  Satoshi Oka ,  Masatake Katayama

发明人： Norihiro Kobayashi ,  Kazuo Mamada ,  Yuichi Matsumoto ,  Satoshi Oka ,  Masatake Katayama

IPC分类号： H01L21/22 ,  H01L21/31 ,  H01L21/673 ,  H01L21/302

CPC分类号： C04B41/87 ,  C04B41/5066 ,  C04B41/52 ,  C04B41/89 ,  C30B35/00

摘要： A silicon nitride layer 12b is thermally grown on the topmost surface of the heat treatment jig 12 composed of silicon or silicon carbide in a nitrogen ambience. The silicon nitride layer 12b is thermally grown in a nitrogen ambience in the temperature range of 1,100.degree. C.-1,300.degree. C. It is desirable to remove slightly the surface of the jig by, for example, hydrogen etching before thermally growing the silicon nitride layer 12b. After the etching, a silicon oxide layer can be thermally grown on the jig surface in an oxygen ambience before thermally growing the silicon nitride layer 12b.

摘要翻译： 氮化硅层12b在氮气氛中由硅或碳化硅构成的热处理夹具12的最上表面热生长。 氮化硅层12b在1100℃-1300℃的温度范围内在氮气气氛中热生长。期望通过例如在将氮化硅热生长之前的氢蚀刻稍微去除夹具的表面 层12b。 在蚀刻之后，在氧化氮化物层12b热生长之前，可以在氧气氛中在夹具表面上热生长氧化硅层。