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公开(公告)号：US20070252172A1
公开(公告)日：2007-11-01
申请号：US11741305
申请日：2007-04-27
IPC分类号： H01L31/00
CPC分类号： H01L29/7828 , H01L29/0623 , H01L29/0653 , H01L29/0847 , H01L29/1033 , H01L29/1608 , H01L29/267 , H01L29/36 , H01L29/4236 , H01L29/45 , H01L29/456 , H01L29/8618
摘要： A semiconductor device, includes: 1) a semiconductor base having a first face; 2) a hetero semiconductor region configured to contact the first face of the semiconductor base and different from the semiconductor base in band gap, the semiconductor base and the hetero semiconductor region defining therebetween a junction part in the hetero semiconductor region, a concentration of an impurity introduced in at least a first certain region including the junction part being less than or equal to a solid solution limit to a semiconductor material included in the hetero semiconductor region; 3) a gate electrode formed, via a gate insulation film, in a certain position adjacent to the junction part; 4) a source electrode configured to be connected to the hetero semiconductor region; and 5) a drain electrode configured to be connected to the semiconductor base.
摘要翻译： 一种半导体器件，包括：1）具有第一面的半导体基底; 2）异质半导体区域，被配置为在带隙中接触半导体基底的第一面并且不同于半导体基底，半导体基底和异质半导体区域在其间限定异质半导体区域中的接合部分，杂质浓度 引入至少包括所述接合部分的第一特定区域小于或等于包含在所述异质半导体区域中的半导体材料的固溶极限; 3）通过栅极绝缘膜在与所述接合部分相邻的特定位置处形成的栅电极; 4）构造成连接到所述异质半导体区域的源电极; 以及5）被配置为连接到所述半导体基底的漏电极。
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公开(公告)号：US20070221955A1
公开(公告)日：2007-09-27
申请号：US11724389
申请日：2007-03-15
IPC分类号： H01L29/739
CPC分类号： H01L29/7828 , H01L21/0273 , H01L21/32139 , H01L29/1608 , H01L29/267 , H01L29/4236 , H01L29/66068
摘要： A trench is formed extending from a surface of a hetero semiconductor region of a polycrystal silicon to the drain region. Further, a driving point of the field effect transistor, where a gate insulating film, the hetero semiconductor region and the drain region are adjoined, is formed at a position spaced apart from a side wall of the trench.
摘要翻译： 形成从多晶硅的异质半导体区域的表面延伸到漏极区域的沟槽。 此外，栅极绝缘膜，异质半导体区域和漏极区域相邻的场效应晶体管的驱动点形成在与沟槽的侧壁间隔开的位置处。
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公开(公告)号：US20070218596A1
公开(公告)日：2007-09-20
申请号：US11374418
申请日：2006-03-14
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L29/66068 , H01L21/8213 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/1608 , H01L29/267 , H01L29/41741 , H01L29/41766 , H01L29/4236 , H01L29/7828
摘要： A method of manufacturing a semiconductor device is disclosed. The semiconductor device includes a semiconductor body of a first conductivity type, a hetero semiconductor region adjacent to one main surface of the semiconductor body and having a band gap different from that of the semiconductor body, and a gate electrode formed in a junction portion between the hetero semiconductor region and the semiconductor body through a gate insulating film. The method includes a first process of forming a predetermined trench by using a mask layer having a predetermined opening on one main surface side of the semiconductor body, a second process of forming a buried region adjacent to at least a side wall of the trench and so as to extend from the trench, a third process of forming a hetero semiconductor layer so as to adjoin the semiconductor body and the buried region, and a fourth process of forming the hetero semiconductor region by patterning the hetero semiconductor layer.
摘要翻译： 公开了制造半导体器件的方法。 半导体器件包括第一导电类型的半导体本体，与半导体本体的一个主表面相邻且具有与半导体本体不同的带隙的异质半导体区域，以及形成在该半导体器件之间的接合部分中的栅电极 异质半导体区域和半导体本体通过栅极绝缘膜。 该方法包括通过使用在半导体主体的一个主表面侧上具有预定开口的掩模层来形成预定沟槽的第一工艺，形成与沟槽的至少侧壁相邻的掩埋区域的第二工艺 从沟槽延伸，形成与半导体本体和掩埋区相邻的异质半导体层的第三工序，以及通过图案化杂半导体层形成异质半导体区的第四工序。
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公开(公告)号：US20070181886A1
公开(公告)日：2007-08-09
申请号：US11701429
申请日：2007-02-02
IPC分类号： H01L31/0312
CPC分类号： H01L29/267 , H01L29/0619 , H01L29/0623 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A semiconductor device, includes: a first conductivity-semiconductor substrate; a hetero semiconductor region for forming a hetero junction with the first conductivity-semiconductor substrate; a gate electrode adjacent to a part of the hetero junction by way of a gate insulating film; a drain electrode connecting to the first conductivity-semiconductor substrate; a source electrode connecting to the hetero semiconductor region; and a second conductivity-semiconductor region formed on a part of a first face of the first conductivity-semiconductor substrate in such a configuration as to oppose the gate electrode via the gate insulating film, the gate insulating film, the hetero semiconductor region and the first conductivity-semiconductor substrate contacting each other to thereby form a triple contact point. A first face of the second conductivity-semiconductor region has such an impurity concentration that allows a field from the gate electrode to form an inversion layer on the first face of the second conductivity-semiconductor region.
摘要翻译： 一种半导体器件，包括：第一导电半导体衬底; 用于与第一导电半导体衬底形成异质结的异质半导体区域; 通过栅绝缘膜与所述异质结的一部分相邻的栅电极; 连接到所述第一导电半导体衬底的漏电极; 连接到所述异质半导体区域的源电极; 以及第二导电半导体区域，形成在第一导电半导体基板的第一面的一部分上，以与栅电极相对的方式经由栅极绝缘膜，栅极绝缘膜，异质半导体区域和第一导电半导体区域 导电性半导体基板彼此接触，从而形成三重接触点。 第二导电率半导体区域的第一面具有允许来自栅电极的场在第二导电半导体区域的第一面上形成反型层的杂质浓度。
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公开(公告)号：US20060220061A1
公开(公告)日：2006-10-05
申请号：US11444433
申请日：2006-06-01
IPC分类号： H01L31/00
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66712 , H01L29/66734 , H01L29/7813 , H01L29/8083
摘要： A semiconductor device of the invention includes a first conductive type semiconductor base substrate; and a switching mechanism which is formed on a first main surface of the semiconductor base substrate and switches ON/OFF of a current. In the semiconductor base substrate, a plurality of columnar hetero-semiconductor regions are formed at spaced intervals within the semiconductor substrate, and the hetero-semiconductor regions are made of a semiconductor material having a different band gap from the semiconductor substrate and extend between the first main surface and a second main surface opposite to the first main surface.
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公开(公告)号：US20060060917A1
公开(公告)日：2006-03-23
申请号：US11217615
申请日：2005-09-02
IPC分类号： H01L29/76
CPC分类号： H01L29/1608 , H01L29/267 , H01L29/66068 , H01L29/7827
摘要： An aspect of the present invention provides a method of manufacturing a semiconductor device, the method including a first process to form a second hetero-semiconductor layer on a principal surface of the semiconductor base, a second process to etch selectively the second hetero-semiconductor layer to form the second hetero-semiconductor region employing a mask layer provided with a predetermined opening, a third process to form employing the mask layer, a first hetero-semiconductor layer, a fourth process to etch selectively the first hetero-semiconductor layer to form the first hetero-semiconductor region, and a fifth process to form the gate insulating film in contact with the first hetero-semiconductor region and the semiconductor base.
摘要翻译： 本发明的一个方面提供一种制造半导体器件的方法，所述方法包括在所述半导体基底的主表面上形成第二异质半导体层的第一工艺，选择性地蚀刻所述第二异质半导体层的第二工艺 以形成第二异质半导体区域，采用设置有预定开口的掩模层，第三种形成采用掩模层的工艺，第一异质半导体层，选择性地蚀刻第一异质半导体层以形成第二异质半导体层的第四工艺 第一异质半导体区域和形成与第一异质半导体区域和半导体基底接触的栅极绝缘膜的第五工序。
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公开(公告)号：US06580625B2
公开(公告)日：2003-06-17
申请号：US10086834
申请日：2002-03-04
IPC分类号： H02M324
CPC分类号： H03K17/605 , H02M1/08 , H03K17/04213 , H03K17/666
摘要： There are included a switching circuit for flowing pulse electrical current through a primary winding of a transformer, a half wave rectification circuit or a full wave rectification circuit for extracting electrical current from a secondary winding of the transformer while this pulse electrical current flows, and an electrical current regulation circuit which controls the magnitude of the electrical current which is extracted from the secondary winding of the transformer according to the collector voltage of the power transistor. Since the most suitable pulse electrical current is made directly from the direct current power supply and is supplied to the base of the power transistor, there is no requirement to provide any DC-DC converter, and it is possible to reduce the size and the cost of the power supply circuit for driving the power transistor.
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