公开(公告)号：US06853600B2

公开(公告)日：2005-02-08

申请号：US10684497

申请日：2003-10-15

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： G11C11/22 ,  G11C7/02 ,  G11C7/14

CPC分类号： G11C11/22 ,  G11C7/14

摘要： A dummy cell (reference electric potential generating circuit) DC has a paraelectric capacitor DCC1 and a ferro-electric capacitor DCC2. One end of the paraelectric capacitor DCC1 and one end of the ferro-electric capacitor DCC2 are commonly connected to a node N1. A dummy plate electric potential DPL1 is supplied to the other end of the paraelectric capacitor DCC1, and a dummy plate electric potential DPL2 is supplied to the other end of the ferro-electric capacitor DCC2. When data of a memory cell MC is read at a bit line (selective bit line) BL1, a reference electric potential is supplied to a bit line (reference bit line) BL2 from the dummy cell DC.

摘要翻译： 虚拟单元（参考电位产生电路）DC具有顺电电容器DCC1和铁电电容器DCC2。 顺电电容器DCC1的一端和铁电电容器DCC2的一端通常连接到节点N1。 向平路电容器DCC1的另一端供给虚拟板电位DPL1，向铁电电容器DCC2的另一端供给虚拟板电位DPL2。 当在位线（选择位线）BL1读取存储单元MC的数据时，将参考电位从虚拟单元DC提供给位线（参考位线）BL2。

公开(公告)号：US06404274B1

公开(公告)日：2002-06-11

申请号：US09289413

申请日：1999-04-09

申请人： Koji Hosono ,  Yasuo Itoh ,  Ken Takeuchi

发明人： Koji Hosono ,  Yasuo Itoh ,  Ken Takeuchi

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  G11C16/30 ,  H02M2001/0025

摘要： There is provided an internal voltage generating circuit for outputting positive multi-level voltages by using a current addition type D/A conversion circuit, and suppressing increase of the pattern area of a resistor network even if the number of bits of a digital input increases. This circuit includes a load resistor element having one terminal connected to the output node of a voltage generating circuit, a first voltage setting circuit which is connected to a first node to which the other terminal of the load resistor element is connected and controls the magnitude of an input current from the load resistor element by controlling an equivalent resistor in accordance with digital data, a second voltage setting circuit which is connected to the first node and into which a predetermined current flows from the load resistor element, a potential comparison circuit for detecting a potential at the first node by comparing the potential at the first node with a reference potential, and a voltage control circuit for setting the potential at the first node to become equal to the reference potential by substantially controlling the voltage generating circuit in accordance with an output from the circuit.

摘要翻译： 提供了一种内部电压产生电路，用于通过使用电流相加型D / A转换电路输出正的多电平电压，并且即使数字输入的位数增加，也抑制了电阻网络的图形区域的增加。 该电路包括负载电阻元件，其一端连接到电压产生电路的输出节点，第一电压设置电路连接到负载电阻元件的另一端连接到的第一节点， 通过根据数字数据控制等效电阻器，来自负载电阻元件的输入电流;连接到第一节点的第二电压设置电路，预定电流从负载电阻器元件流过的电压设定电路;用于检测的电位比较电路 通过将第一节点处的电位与参考电位进行比较来确定第一节点处的电位;以及电压控制电路，用于通过基本上控制电压产生电路来将第一节点处的电位设置为等于参考电位 从电路输出。

公开(公告)号：US6107658A

公开(公告)日：2000-08-22

申请号：US468928

申请日：1999-12-22

申请人： Yasuo Itoh ,  Koji Sakui

发明人： Yasuo Itoh ,  Koji Sakui

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/72

CPC分类号： H01L27/115 ,  G11C16/0483

摘要： In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

摘要翻译： 在使用本地自增强系统的NAND EEPROM中，将允许与所选存储单元相邻的存储单元导通的中间电压被施加到相邻存储单元的控制栅极。 因此，即使相邻的存储单元处于常关状态，也可以将位线的电位发送到相邻的存储单元。 因此，提高了在非选择的NAND存储单元列中写入禁止的可靠性，同时可以将数据随机写入到所选NAND存储单元列中的多个存储单元中。 当要擦除数据时，施加到控制栅极的擦除电压的绝对值可以较小。 结果，可以通过比传统技术中所需的更低的擦除电压来擦除数据。 因此，可以进一步提高元素精化，可靠性和产率。

公开(公告)号：US6061289A

公开(公告)日：2000-05-09

申请号：US406731

申请日：1999-09-28

申请人： Yasuo Itoh ,  Sumio Tanaka

发明人： Yasuo Itoh ,  Sumio Tanaka

IPC分类号： G11C16/06 ,  H03M1/68 ,  H03M1/74 ,  H03M1/76 ,  H03M1/78 ,  G11C7/00 ,  G11C16/04

CPC分类号： H03M1/68 ,  H03M1/785 ,  H03M1/76

摘要： A variable potential generating circuit includes a resistive potential divider circuit and first and second operational amplifiers. The resistive potential divider circuit includes a switching element and a current-scaling type digital/analog converter circuit connected in series between a power supply node and a ground node. The resistive potential divider circuit has a first node at which a divided potential obtained by resistive division of a variable potential to be output from a variable potential output node appears and a second node to which a virtual potential is applied. The first operational amplifier compares the divided potential of the first node with a reference potential to effect the feedback control for setting the variable output potential equal to the reference potential. The second operational amplifier compares the virtual potential of the second node with the reference potential to effect the feedback control for setting the virtual potential equal to the reference potential.

摘要翻译： 可变电位发生电路包括电阻分压器电路和第一和第二运算放大器。 电阻分压器电路包括在电源节点和接地节点之间串联连接的开关元件和电流调节型数字/模拟转换器电路。 电阻分压器电路具有第一节点，在该第一节点处出现通过对从可变电位输出节点输出的可变电位的电阻划分获得的分压电位和施加虚拟电位的第二节点。 第一运算放大器将第一节点的分压电位与参考电位进行比较，以实现用于设置等于参考电位的可变输出电位的反馈控制。 第二运算放大器将第二节点的虚拟电位与参考电位进行比较，以实现用于设置虚拟电位等于参考电位的反馈控制。

公开(公告)号：US6016274A

公开(公告)日：2000-01-18

申请号：US044989

申请日：1998-03-20

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454 ,  G11C5/147

摘要： The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied. The control circuit controls the dividing circuit such as to set the write voltage indicated by the write voltage data in the memory element in the write mode. Thus, the write voltage is optimized, and the appropriate number of times of write can be performed.

摘要翻译： 本发明的半导体存储器件包括具有浮置栅极和控制栅极的存储单元，用于通过偏移阈值来保持数据。 在测试模式下，通过验证电路验证从存储单元读取的数据。 如果验证结果未被批准，则再次执行数据写入。 这种写入的次数由计数电路计数。 在数据表中，存储写入和写入电压次数之间的各种相关性。 从数据表中选择性地输出与计数电路的写入次数对应的写入电压数据。 写入电压将写入电压数据写入存储元件。 用于改变写入电压的电压限制电路另一端的电压被分成几个电压，因此可以改变写入电压。 控制电路控制分频电路，以将写入电压数据所指示的写入电压设置在写入模式中的存储元件中。 因此，写入电压被优化，并且可以执行适当的写入次数。

公开(公告)号：US5990977A

公开(公告)日：1999-11-23

申请号：US845705

申请日：1997-04-25

申请人： Isami Kaneda ,  Yasuo Itoh

发明人： Isami Kaneda ,  Yasuo Itoh

IPC分类号： H04N5/78 ,  H04N5/262 ,  H04N5/775 ,  H04N5/85 ,  H04N5/91 ,  H04N9/74 ,  H04N9/804

CPC分类号： H04N9/74 ,  H04N9/8042 ,  H04N5/445 ,  H04N5/775 ,  H04N5/85

摘要： A picture switching apparatus for executing a fade-out/fade-in processing between adjacent video recording files includes a multiplier for multiplying a decoded video data with a multiplication coefficient (1-km), a multiplier for multiplying an output data of a data output circuit with a multiplication coefficient km and a data synthesizer for summing results of multiplication from the respective multipliers. The picture switching apparatus thus constructed performs the fade-out/fade-in processing without modification of the original video data for fading processing, by controlling km at the junction between the files such that the mining ratio of the color data for fading to a decoded color data is gradually increased/decreased.

摘要翻译： 一种用于在相邻视频记录文件之间执行淡出/淡入淡出处理的画面切换装置，包括用于将解码视频数据与乘法系数（1-km）相乘的乘法器，用于将数据输出的输出数据相乘的乘法器 具有乘法系数km的电路和用于对来自相应乘法器的乘法结果求和的数据合成器。 这样构成的图像切换装置通过控制文件之间的连接处的km，使得淡入淡出的彩色数据的采样率与经解码的图像切换装置进行淡入/淡出处理，而不改变用于衰落处理的原始视频数据 颜色数据逐渐增加/减少。

公开(公告)号：US5784315A

公开(公告)日：1998-07-21

申请号：US402055

申请日：1995-03-10

申请人： Yasuo Itoh

发明人： Yasuo Itoh

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C16/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3454 ,  G11C5/147

摘要： The semiconductor memory device of the present invention includes a memory cell having a floating gate and a control gate, for maintaining data by shifting the threshold value. In the test mode, the data read from the memory cell is verified by the verify circuit. If the result of verify is not approved, the writing of data is carried out again. The number of times of such writing is counted by the count circuit. In the data table, various correlations between the numbers of times of write and write voltages are stored. The write voltage data corresponding to the number of times of write from the count circuit is selectively output from the data table. The write voltage data is written in the memory element by the write circuit. The voltage at the other terminal of the voltage limiting circuit for varying the write voltage, is divided into several voltages, and thus the write voltage can be varied. The control circuit controls the dividing circuit such as to set the write voltage indicated by the write voltage data in the memory element in the write mode. Thus, the write voltage is optimized, and the appropriate number of times of write can be performed.

公开(公告)号：US4748596A

公开(公告)日：1988-05-31

申请号：US792197

申请日：1985-10-28

申请人： Mitsugi Ogura ,  Yasuo Itoh

发明人： Mitsugi Ogura ,  Yasuo Itoh

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/34 ,  G11C11/401 ,  G11C11/4091 ,  G11C7/00

CPC分类号： G11C7/065 ,  G11C11/4091

摘要： In a dynamic semiconductor memory, bit line pairs and word lines are perpendicular to each other and arranged in a matrix constituted by memory cells. Dummy cells are arranged at intersections between the bit line pairs and a pair of dummy cell word lines. The capacitance of each dummy cell is half that of the memory cell. A pre-sense amplifier and a main sense amplifier are arranged in each pair of bit lines. When data is read out from a selected memory cell, the pre-sense amplifiers are simultaneously activated to perform the pre-sensing operation. However, in the main sensing operation, only one specific main sense amplifier arranged in a certain bit line pair including the bit line connected to the selected memory cell is activated.

摘要翻译： 在动态半导体存储器中，位线对和字线彼此垂直并且以由存储器单元构成的矩阵布置。 虚拟单元被布置在位线对和一对虚拟单元字线之间的交点处。 每个虚拟单元的电容是存储单元的一半。 在每对位线中布置预读放大器和主读出放大器。 当从所选择的存储单元读出数据时，预读放大器同时被激活以执行预感测操作。 然而，在主感测操作中，仅激活布置在包括连接到所选择的存储器单元的位线的某一位线对中的一个特定主读出放大器。

公开(公告)号：US4719618A

公开(公告)日：1988-01-12

申请号：US737000

申请日：1985-05-23

申请人： Yasuo Itoh ,  Yuisuke Maruyama

发明人： Yasuo Itoh ,  Yuisuke Maruyama

IPC分类号： H04M3/56 ,  H04J3/02

CPC分类号： H04M3/561

摘要： A digital conference circuit for multiplexed voice signals. Each slot for each of the users is further sub-divided into sub-slots for all the users. A selection circuit indicates which originating users are to be connected with which receiving users within a conference. No message is retransmitted to the originator. The received message in a slot is gated according to the selection signal into an adder, also receiving the output of a shift register holding the signals for all sub-slots in one slot. The added signal is shifted into the shift register. Once all the corresponding sub-slots have been added, the output of the shift register is transmitted to the users.

摘要翻译： 一种用于复用语音信号的数字会议电路。 每个用户的每个时隙进一步细分为所有用户的子时隙。 选择电路指示哪个起始用户将与会议内的哪个接收用户连接。 没有消息被重新发送到发起者。 根据选择信号将时隙中的接收到的消息选通到加法器中，同时接收保持一个时隙中所有子时隙的信号的移位寄存器的输出。 添加的信号被移入移位寄存器。 一旦添加了所有相应的子时隙，则移位寄存器的输出被传送给用户。

公开(公告)号：US4534980A

公开(公告)日：1985-08-13

申请号：US633139

申请日：1984-07-23

申请人： Yasuo Itoh ,  Hideo Kato ,  Kugako Matsumura ,  Tomoyasu Nishikawa ,  Akira Hisano ,  Takehisa Yamada ,  Eiichi Koshinaka

发明人： Yasuo Itoh ,  Hideo Kato ,  Kugako Matsumura ,  Tomoyasu Nishikawa ,  Akira Hisano ,  Takehisa Yamada ,  Eiichi Koshinaka

IPC分类号： A61K9/06 ,  A61K9/00 ,  A61K31/165 ,  A61K31/19 ,  A61K47/00 ,  A61K47/16 ,  A61K47/18 ,  A61P17/00 ,  A61P25/04 ,  A61P29/00

CPC分类号： A61K9/0014 ,  A61K31/165 ,  A61K31/19 ,  A61K47/18 ,  Y10S514/871

摘要： Creams for external or topical use comprising ketoprofen as an effective component and crotamiton as an agent for preventing crystalline precipitation of the effective component. The creams possess an antiinflammatory and antipyretic effect and are excellent in permeation and absorption into the skin which enables the topical and external use of the creams.

摘要翻译： 用于外用或局部用途的霜剂，其包含酮洛芬作为有效成分，克罗他米通作为用于防止有效成分的结晶沉淀的试剂。 乳霜具有抗炎和解热作用，并且在皮肤中的渗透和吸收优异，能够局部和外部使用霜剂。